library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity counter is
port(clk,clk1,en,clr:in std_logic;
ledout:out std_logic_vector(6 downto 0); scanout:out std_logic_vector(1 downto 0); co:out std_logic); end counter;
architecture a of counter is
signal cnt:std_logic_vector(7 downto 0); signal led:std_logic_vector(6 downto 0); signal scan:std_logic:='0';
signal hex:std_logic_vector(3 downto 0); begin
process(clk) begin
if(clk'event and clk='1')then if en='1'then if clr='1'then
cnt<=(others=>'0'); else
if cnt=\"00111111\"then cnt<=\"00000000\"; co<='1'; else
cnt<=cnt+'1'; co<='0'; end if; end if; end if; end if; end process; process(clk1) begin
if clk1'event and clk1='1'then scan<=not scan; end if; end process; ledout<= not led;
scanout<=\"10\" when scan='0' else \"01\";
hex<=cnt(7 downto 4) when scan='1'else cnt(3 downto 0);
with hex select
led<=\"1111001\"when\"0001\ \"0100100\"when\"0010\ \"0110000\"when\"0011\ \"0011001\"when\"0100\ \"0010010\"when\"0101\ \"0000010\"when\"0110\ \"1111000\"when\"0111\ \"0000000\"when\"1000\ \"0010000\"when\"1001\ \"0001000\"when\"1010\ \"0000011\"when\"1011\ \"1000110\"when\"1100\ \"0100001\"when\"1101\ \"0000110\"when\"1110\ \"0001110\"when\"1111\ \"1000000\"when others; end a;
2、设计一个带计数使能、异步复位、带进位输出的增1二十进制计数器，计数结果由共阴极七段数码管显示。
library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity da is
Port ( clk : in STD_LOGIC; clk1 : in STD_LOGIC; clr : in STD_LOGIC; en : in STD_LOGIC; co : out STD_LOGIC;
ledout : out STD_LOGIC_VECTOR (6 downto 0); sel : out STD_LOGIC_VECTOR (1 downto 0)); end da;
architecture ehavioral of da is
signal cnt:std_logic_vector(7 downto 0):=\"00000000\"; signal led:std_logic_vector(6 downto 0); signal scan:std_logic:='0';
signal hex:std_logic_vector(3 downto 0); begin
process(clk,clr) begin
if clr='1'then
cnt<=(others=>'0');
elsif clk'event and clk='1' then
if en='1'then
if cnt=\"00001001\"then cnt<=\"00010000\"; co<='0';
elsif cnt=\"00011001\"then cnt<=\"00000000\"; co<='1'; else
cnt<=cnt+'1'; co<='0'; end if; end if; end if; end process; process(clk1) begin
if clk1'event and clk1='1'then scan<=not scan; end if; end process;
hex<=cnt(7 downto 4) when scan='1'else cnt(3 downto 0); with hex select
led<=\"1111001\"when\"0001\ \"0100100\"when\"0010\ \"0110000\"when\"0011\ \"0011001\"when\"0100\ \"0010010\"when\"0101\ \"0000010\"when\"0110\ \"1111000\"when\"0111\ \"0000000\"when\"1000\ \"0010000\"when\"1001\
\"1000000\"when\"0000\ \"1111111\"when others; ledout<= not led; sel<=\"10\" when scan='0' else \"01\"; end ehavioral;
3、设计一个带计数使能、同步复位、同步装载的可逆七位二进制计数器，计数结果由共阴极七段数码管显示。
library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity counter is
port(clk,clks,clr,en,stld,dir:in std_logic; din:in std_logic_vector(6 downto 0);
ledout:out std_logic_vector(6 downto 0); scanout:out std_logic_wector(1 downto 0); end counter;
architecture a of counter is
signal cnt:std_logic_vector(6 downto 0); signal led:std_logic_vector(6 downto 0); signal scan:std_logic;
signal hex:std_logic_vector(3 downto 0); begin
process(clk,clr) begin
if clk'event and clk='1'then if clr='1' then
cnt<=(others=>'0'); else
if stld='0' then cnt<=din;
elsif en='1' then if dir='1' then
if cnt =”01111111” then cnt <= “00000000”; co<=’1’; else cnt <= cnt + 1; end if; else
if cnt =”00000000” then cnt <= “01111111”; co<=’1’; else cnt <= cnt - 1;
end if; end if; end if; end if; End if;
end process; process(clks) begin
if clks'event and clks='1'then scan<=not scan; end if; end process; ledout<=not led;
scanout<=\"10\" when scan='0' else \"01\";
hex<='0'&cnt(6 downto 4) when scan='1' else cnt(3 downto 0); with hex select
led<= \"1111001\"when \"0001\ \"0100100\"when \"0010\ \"0110000\"when \"0011\ \"0011001\"when \"0100\ \"0010010\"when \"0101\ \"0000010\"when \"0110\ \"1111000\"when \"0111\ \"0000000\"when \"1000\ \"0010000\"when \"1001\ \"0001000\"when \"1010\ \"0000011\"when \"1011\ \"1000110\"when \"1100\ \"0100001\"when \"1101\ \"0000110\"when \"1110\ \"0001110\"when \"1111\ \"1000000\"when others; End a ;
4、设计一个带计数使能、异步复位、异步装载、可逆计数的通用计数器。计数结果由共阴极七段数码管显示。 library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity counter is
generic(count_value:integer:=9); port(clk,clr,en,load,dir:in std_logic;
data_in:in integer range 0 to count_value; count:out integer range 0 to count_value; ledout:out std_logic_vector(6 downto 0)); end counter;
architecture a of counter is
signal cnt:integer range 0 to count_value; signal led:std_logic_vector(6 downto 0); begin
process(load,clk) begin
if clr='1' then cnt<=0; else
if load='1' then cnt<=data_in; elsif(clk'event and clk='1') then if en='1' then
if dir='1' then
if cnt=count_value then cnt<=0; else
cnt<=cnt+1; end if; else
if cnt=0 then
cnt<=count_value; else cnt<=cnt-1; end if; end if; end if; end if; end if; end process; count<=cnt; ledout<=not led; with cnt select
led<= \"1111001\"when 1, \"0100100\"when 2, \"0110000\"when 3, \"0011001\"when 4, \"0010010\"when 5, \"0000010\"when 6, \"1111000\"when 7, \"0000000\"when 8, \"0010000\"when 9, \"1000000\"when 0, \"1111111\"when others; End a;
5、设计一个具有16分频、8分频、4分频和2分频功能的分频器
library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all;
entity clkdiv is port(clk:in std_logic; clk_div2:out std_logic; clk_div4:out std_logic; clk_div8:out std_logic;
clk_div16:out std_logic); end clkdiv;
architecture rtl of clkdiv is
signal count:std_logic_vector(3 downto 0); begin process(clk) begin
if (clk'event and clk='1') then if(count=\"1111\" )then count<=(others=>'0'); else
count<=count+1; end if; end if; end process; clk_div2<=count(0); clk_div4<=count(1); clk_div8<=count(2); clk_div16<=count(3); end rtl;
6、设计一个正负脉宽相等的通用分频器
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY counter IS
GENERIC( count_value: INTEGER:=15); PORT (clk,clr,en: IN STD_LOGIC; count:OUT STD_LOGIC); END counter;
ARCHITECTURE a OF counter IS
SIGNAL cnt: INTEGER RANGE 0 TO count_value; SIGNAL co: STD_LOGIC; SIGNAL count1:STD_LOGIC; BEGIN
PROCESS (clk,clr) BEGIN IF clr = '1' THEN cnt <= 0; ELSIF (clk'EVENT AND clk = '1') THEN IF en = '1' THEN IF cnt = count_value THEN
cnt <= 0; co<='1'; ELSE
cnt <= cnt + 1; co<='0'; END IF; END IF; END IF; END PROCESS; PROCESS(co ) BEGIN
IF( co'EVENT AND co = '1')THEN count1<=NOT count1; END IF;
count<=count1; END PROCESS; END a;
7、设计一个正负脉宽可控的16分频的分频器
library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity fen_pin is port(clk:in std_logic;
din:in std_logic_vector(1 downto 0); count:out std_logic); end fen_pin;
architecture behave of fen_pin is signal co:std_logic; begin
count<=co; process(clk)
variable cnt:std_logic_vector(3 downto 0); begin
if(clk'event and clk='1')then if(cnt= \"1111\") then cnt:=\"0000\"; co<=not co;
elsif(cnt=din)then co<=not co; cnt:=cnt+'1'; else cnt:=cnt+'1'; end if; end if;
end process;
end behave;
8、根据需要设计一个分频器：可以控制实现四种分频形式：第一种：8分频、第二种：10分频、第三种：15分频、第四种：16分频，其中8分频和16分频为正负脉宽相等的分频器
library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity fenpin is
port(clk:in std_logic;
en:in std_logic_vector(1 downto 0); cout:out std_logic;
ledout:out std_logic_vector(6 downto 0)); end fenpin;
architecture dgnfenpin of fenpin is signal led:std_logic_vector(6 downto 0); signal hex:std_logic_vector(3 downto 0); begin process(clk)
variable cnt:std_logic_vector(3 downto 0); begin
if(clk'event AND clk='1')then if(en=\"00\")then if(cnt>=\"1000\")then cnt:=\"0000\"; else
cnt:=cnt+'1'; end if; cout<=cnt(2); elsif(en=\"01\")then if(cnt>=\"1010\")then cnt:=\"0000\"; cout<='1'; else
cnt:=cnt+'1'; cout<='0'; end if; elsif(en=\"10\")then if(cnt>=\"1110\")then cnt:=\"0000\";cout<='1'; else
cnt:=cnt+'1';cout<='0'; end if; else
if(cnt>=\"1111\")then cnt:=\"0000\"; else
cnt:=cnt+'1'; end if; cout<=cnt(3); end if; end if; end process; ledout<=not led; with en select
led<=\"0000000\"when\"00\ \"0001000\"when\"01\ \"0001110\"when\"10\ \"1000000\"when\"11\ \"1111111\"when others; end dgnfenpin;
9、设计一个M序列发生器，M序列为“11100111”
LIBRARY IEEE;
USE IEEE.STD_logic_1164.all;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY SEQ IS
PORT(CLK:IN STD_logic;
FOUT:OUT STD_logic); END SEQ;
ARCHITECTURE BEHAVE OF SEQ IS
SIGNAL CNT:STD_logic_VECTOR(2 DOWNTO 0); BEGIN
PROCESS(CLK) BEGIN
IF CLK'EVENT AND CLK='1' THEN IF CNT=\"111\" THEN CNT<=\"000\"; ELSE
CNT<=CNT+'1'; END IF; END IF;
END PROCESS;
WITH CNT SELECT FOUT<='1' WHEN \"000\'1' WHEN \"001\'1' WHEN \"010\'0' WHEN \"011\'0' WHEN \"100\'1' WHEN \"101\'1' WHEN \"110\'1' when \"111\
'0' WHEN OTHERS; end BEHAVE;
10、设计一个彩灯控制器，彩灯共有21个，每次顺序点亮相邻的3个彩灯，如此循环执行，循环的方向可以控制
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all; entity caideng is
port(clk,reset:in std_logic;
l_r:in std_logic; ----控制循环方向；
output:out std_logic_vector(15 downto 0));---输出 end entity;
architecture art of caideng is
signal q:std_logic_vector(15 downto 0); begin
process(clk,reset,l_r,q) begin
if reset='1' then
q<=\"0000000000000000\";
elsif clk'event and clk='1' then
if l_r='1' then ----表示向右循环； if q=\"0000000000000000\" then q<=\"1110000000000000\"; else q<=q(0)&q(15 downto 1); end if;
else ----向左循环;
if q=\"0000000000000000\" then q<=\"0000000000000111\"; else q<=q(14 downto 0)&q(15);
end if;
end if; end if; output<=q; end process; end art;
11、设计一个具有左移、右移控制，同步并行装载和串行装载的8位串行移位寄存器
library ieee;
use ieee.std_logic_1164.all; entity shifter is port(clr:in std_logic; clk:in std_logic; ser:in std_logic;
clkin:in std_logic; stld:in std_logic;
din:in std_logic_vector(0 to 7); en:in std_logic; qh:out std_logic); end shifter;
architecture rt1 of shifter is
signal reg:std_logic_vector(0 to 7); signal aa:std_logic; begin
process(clk,clr) begin
if clr='1' then reg<=(others=>'0'); aa<=reg(7);
elsif clk'event and clk='1' then if clkin='0' then if stld='0'then reg<=din; else
if en='1' then reg<=ser®(0 to 6); aa<=reg(7);
elsif en='0' then
reg<=reg(1 to 7)&ser;
aa<=reg(0); end if; end if; end if; end if;
end process; qh<=aa; end rt1;
12、设计一个15人表决电路，参加表决者为15人，同意为1，不同意为0，同意者过半则表决通过，绿指示灯亮，表决不通过则红指示灯亮。数码管显示赞成人数。
library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity selector is
port(a:in std_logic_vector(14 downto 0); r,g:out std_logic;
ledout:out std_logic_vector(6 downto 0)); end selector;
architecture rt1 of selector is
signal led:std_logic_vector(6 downto 0); signal count:std_logic_vector(3 downto 0); begin
process(a)
variable cnt:std_logic_vector(3 downto 0); begin
cnt:=\"0000\";
for i in 0 to 14 loop if a(i)='1' then cnt:=cnt+1; end if; end loop;
if(cnt>=\"1000\" and cnt<=\"1110\")then g<='1'; r<='0';
elsif(cnt>=\"0000\"and cnt<=\"0111\")then g<='0'; r<='1'; end if; count<=cnt; end process; ledout<=not led;
with count select
led<=\"1111001\" when \"0001\ \"0100100\" when \"0010\ \"0110000\" when \"0011\ \"0011001\" when \"0100\ \"0010010\" when \"0101\ \"0000010\" when \"0110\ \"1111000\" when \"0111\ \"0000000\" when \"1000\ \"0010000\" when \"1001\ \"1000000\" when others; end rt1;
13、设计一个异步复位，同步并行装载的8位串行左移移位寄存器
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; ENTITY shifter IS
PORT(clk,clr,ser,stld:IN STD_LOGIC; din: IN STD_LOGIC_VECTOR(0 TO 7) ; qh:OUT STD_LOGIC); END shifter;
ARCHITECTURE rt1 OF shifter IS
SIGNAL reg:STD_LOGIC_VECTOR(0 TO 7); begin
process(clk,clr) begin
if clr='1' then
reg<=(others=>'0');
elsif clk'event and clk='1'then if stld='0'then reg<=din; else
reg<=reg(1 to 7)&ser; end if; end if;
end process; qh<=reg(0); end rt1;
14、有16个开关，编号为0到15，编号0的优先级最高。当某一个拨码开关为1时由共阴极七段数码管显示其编号（可用16进制数显示，亦可用十进制显示）
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY bhxs IS
PORT(INPUT:IN STD_LOGIC_VECTOR(15 DOWNTO 0);
LEDOUT: out STD_LOGIC_VECTOR(6 DOWNTO 0)); END bhxs;
ARCHITECTURE RT1 OF bhxs IS
SIGNAL LED:STD_LOGIC_VECTOR(6 DOWNTO 0); BEGIN
process(INPUT) begin
LEDOUT<= LED; IF(INPUT(0)='1')then LED<=\"1000000\";
ELSIF(INPUT(1)='1')then LED<=\"1111001\";
ELSIF(INPUT(2)='1')then LED<=\"0100100\";
ELSIF(INPUT(3)='1')then LED<=\"0110000\";
ELSIF(INPUT(4)='1')then LED<=\"0011001\";
ELSIF(INPUT(5)='1')then LED<=\"0010010\";
ELSIF(INPUT(6)='1')then LED<=\"0000010\";
ELSIF(INPUT(7)='1')then LED<=\"1111000\";
ELSIF(INPUT(8)='1')then LED<=\"0000000\";
ELSIF(INPUT(9)='1')then LED<=\"0010000\";
ELSIF(INPUT(10)='1')then LED<=\"0001000\";
ELSIF(INPUT(11)='1')then LED<=\"0000011\";
ELSIF(INPUT(12)='1')then LED<=\"1000110\";
ELSIF(INPUT(13)='1')then LED<=\"0100001\";
ELSIF(INPUT(14)='1')then LED<=\"0000110\";
ELSIF(INPUT(15)='1')then LED<=\"0001110\"; END IF;
END PROCESS; END RT1;
15、设计一个全自动洗衣机水位控制器。要求：当水位超过某一上限值时，停
止加水，启动洗衣机；当水位低于某一下限值时，加水，停止洗衣机；否则启动洗衣机，停止加水。
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; ENTITY xiyiji IS
PORT(clk,water_high,water_low:IN STD_LOGIC; jiashui,qitong:OUT STD_LOGIC); END xiyiji;
ARCHITECTURE style OF xiyiji IS
TYPE state IS(just_right,too_high,too_low); SIGNAL now_state,next_state:state; BEGIN
PROCESS(now_state,water_high,water_low) BEGIN
CASE now_state IS
WHEN just_right=>jiashui<='0';qitong<='1'; IF water_low='1' THEN next_state<=too_low;
ELSIF water_high='1' THEN next_state<=too_high; ELSE next_state<=just_right; END IF;
WHEN too_low=>jiashui<='1';qitong<='0';
IF water_low='1' THEN next_state<=too_low;
ELSIF water_high='1' THEN next_state<=too_high; ELSE next_state<=just_right; END IF;
WHEN too_high=>jiashui<='0';qitong<='1'; IF water_low='1' THEN next_state<=too_low;
ELSIF water_high='1' THEN next_state<=too_high; ELSE next_state<=just_right; END IF; END CASE; END PROCESS; PROCESS(clk) BEGIN
IF(clk'event AND clk='1')THEN now_state<=next_state; END IF;
END PROCESS; END style;
16、根据真值表设计一位全加器，然后用结构的描述方法设计一个6位加法器。 library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
ENTITY full_adder IS
PORT(a,b,cin:IN STD_LOGIC; s,co:OUT STD_LOGIC); END full_adder;
ARCHITECTURE full_1 of full_adder is
SIGNAL comb:STD_LOGIC_VECTOR(2 downto 0); BEGIN
comb<=a&b&cin; PROCESS(comb) BEGIN
IF(comb=\"000\")then s<='0';co<='0';
elsif(comb=\"001\")then s<='1';co<='0'; elsif(comb=\"100\")then s<='1';co<='0';
elsif(comb=\"010\")then s<='1';co<='0';
elsif(comb=\"011\")then s<='0';co<='1'; elsif(comb=\"101\")then s<='0';co<='1';
elsif(comb=\"110\")then s<='0';co<='1'; else
s<='1';co<='1'; end if;
end process; end full_1;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL; entity full_adder5 is
port( clk: in std_logic; cin:in std_logic;
x,y:in std_logic_vector(5 downto 0);
ledout: out std_logic_vector(6 downto 0); scan_out: out std_logic_vector(1 downto 0); co:out std_logic); end full_adder6;
architecture Behavioral of full_adder6 is component full_adder port(a,b,cin:in std_logic; s,co:out std_logic); end component;
signal z:std_logic_vector(4 downto 0); signal sum: std_logic_vector(5 downto 0); signal scan: std_logic_vector(1 downto 0); signal hex: std_logic_vector(3 downto 0); signal led: std_logic_vector(6 downto 0); begin
uo:full_adder port map(x(0),y(0),cin,sum(0),z(0)); u1:full_adder port map(x(1),y(1),z(0),sum(1),z(1)); u2:full_adder port map(x(2),y(2),z(1),sum(2),z(2)); u3:full_adder port map(x(3),y(3),z(2),sum(3),z(3)); u4:full_adder port map(x(4),y(4),z(3),sum(4),z(4)); u5:full_adder port map(x(5),y(5),z(4),sum(5),co); scan_out<=scan; ledout<=not led; process(clk) begin
if (clk'event and clk='1') then if scan=\"10\" then scan<=\"01\";
else scan<=\"10\"; end if; end if; end process;
hex<=”00”&sum( downto 4)when scan=\"10\" else sum(3 downto 0);with hex select; led<= \"1000000\"when\"0000\ \"1111001\"when\"0001\ \"0100100\"when\"0010\
\"0110000\"when\"0011\ \"0011001\"when\"0100\ --4 \"0010010\"when\"0101\ --5 \"0000010\"when\"0110\ --6 \"1111000\"when\"0111\ --7 \"0000000\"when\"1000\ --8 \"0010000\"when\"1001\ --9 \"0001000\"when\"1010\ --A \"0000011\"when\"1011\ --B \"1000110\"when\"1100\ --C \"0100001\"when\"1101\ --D \"0000110\"when\"1110\ \"0001110\"when\"1111\ --F \"XXXXXXX\"when others;
end Behavioral;
17、设计4位二进制数到BCD码（8421码）的转换器。结果由共阴极数码管显示。
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; use ieee.std_logic_unsigned.all; ENTITY bcd IS PORT(
scanclk:IN STD_LOGIC;
din:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ledout:OUT STD_LOGIC_VECTOR(6 DOWNTO 0); scanout:out integer range 0 to 1 );
END bcd;
ARCHITECTURE a OF bcd IS
signal yh,yl,hex:integer range 0 to 9; signal scan:integer range 0 to 1;
signal led:std_logic_vector(6 downto 0); signal y:integer range 0 to 15; BEGIN
y<=conv_integer(din);
yh<=1 when y>=10 and y<16 else 0; yl<=y when y>=0 and y<10 else (y-10)when y>=10 and y<16 else 0; process(scanclk)
begin
if(scanclk'event and scanclk='1')then if scan=1 then scan<=0; else
scan<=1; end if; end if; end process;
with scan select hex<=yh when 1, yl when others; ledout<=not led; scanout<=scan; with hex select
led<=\"1111001\"when 1, \"0100100\"when 2, \"0110000\"when 3, \"0011001\"when 4, \"0010010\"when 5, \"0000010\"when 6, \"1111000\"when 7, \"0000000\"when 8, \"0010000\"when 9, \"1000000\"when others; END a;
BCD码显示（5个数码管） LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; use ieee.std_logic_unsigned.all; ENTITY bcd IS PORT(
scanclk:IN STD_LOGIC;
din:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ledout:OUT STD_LOGIC_VECTOR(6 DOWNTO 0); scanout:out integer range 0 to 4 );
END bcd;
ARCHITECTURE a OF bcd IS signal scan:integer range 0 to 4;
signal led:std_logic_vector(6 downto 0); signal hex,yh:std_logic;
signal yl:std_logic_vector(3 downto 0);
BEGIN
process(scanclk,din) begin
if(din<=\"1001\")then yh<='0';yl<=din;
elsif(din>\"1001\" and din<=\"1111\")then yh<='1';yl<=din-\"1010\"; end if;
if(scanclk'event and scanclk='1')then if scan=4 then scan<=0; else
scan<=scan+1; end if; end if;
end process;
with scan select hex<=yh when 4, yl(3) when 3,
yl(2) when 2, yl(1) when 1,
yl(0) when others; ledout<=not led; scanout<=scan; with hex select
led<=\"1111001\"when '1', \"1000000\"when others; END A;
18、设计一个跑马灯控制器。一共有8个彩灯，编号为LED0~LED7，点亮方式为：先从左往右顺序点亮，然后从右往左，如此循环往复。
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY lighten IS PORT(
CLK:IN STD_LOGIC;
ledout:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); END lighten;
ARCHITECTURE b OF lighten IS
SIGNAL cnt:STD_LOGIC_VECTOR(3 DOWNTO 0):=\"0000\"; SIGNAL led:STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
PROCESS(CLK) BEGIN
IF(CLK'EVENT AND CLK='1')THEN IF (cnt=\"1101\")THEN cnt<=\"0000\"; ELSE
cnt<=cnt+'1'; END IF;
END IF; END PROCESS; ledout<= not led; WITH cnt SELECT
led<= \"10000000\"WHEN\"0000\ \"01000000\"WHEN\"0001\ \"00100000\"WHEN\"0010\ \"00010000\"WHEN\"0011\ \"00001000\"WHEN\"0100\ \"00000100\"WHEN\"0101\ \"00000010\"WHEN\"0110\ \"00000001\"WHEN\"0111\ \"00000010\"WHEN\"1000\ \"00000100\"WHEN\"1001\ \"00001000\"WHEN\"1010\ \"00010000\"WHEN\"1011\ \"00100000\"WHEN\"1100\ \"01000000\"WHEN\"1101\ \"00000000\"WHEN OTHERS; END b;
19、有8路数据输入，每路数据为4位二进制数，根据不同的控制信号，输出相应的输入数据。同时用由共阴极七段数码管显示输出数据的路号。
library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL; entity mengmeng is
Port ( din1 : in STD_LOGIC_VECTOR (0 to 1); din2 : in STD_LOGIC_VECTOR (0 to 1); din3 : in STD_LOGIC_VECTOR (0 to 1); din4 : in STD_LOGIC_VECTOR (0 to 1); din5 : in STD_LOGIC_VECTOR (0 to 1); din6 : in STD_LOGIC_VECTOR (0 to 1); din7 : in STD_LOGIC_VECTOR (0 to 1);
din8 : in STD_LOGIC_VECTOR (0 to 1); sel : in STD_LOGIC_VECTOR (0 to 2);
ledout : out STD_LOGIC_VECTOR (6 downto 0); dout : out STD_LOGIC_VECTOR (0 to 1)); end mengmeng;
architecture Behavioral of mengmeng is
SIGNAL led:STD_LOGIC_VECTOR(6 downto 0);
begin
dout<=din1 WHEN sel=\"000\" ELSE din2 WHEN sel=\"001\" ELSE din3 WHEN sel=\"010\" ELSE din4 WHEN sel=\"011\" ELSE din5 WHEN sel=\"100\" ELSE din6 WHEN sel=\"101\" ELSE din7 WHEN sel=\"110\" ELSE din8 WHEN sel=\"111\" ELSE (OTHERS=>'0'); ledout<=NOT led; WITH sel SELECT
led<=\"1111001\" WHEN \"000\ \"0100100\" WHEN \"001\ \"0110000\" WHEN \"010\ \"0011001\" WHEN \"011\ \"0010010\" WHEN \"100\ \"0000010\" WHEN \"101\ \"1111000\" WHEN \"110\ \"0000000\" WHEN \"111\ \"1000000\" WHEN others; end Behavioral;
20、设计一个电磁炉控制器：火力控制有三档：煮汤、火锅、煎炒；每种操作都可以设定时间，当时间到自动停火。
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY diancilu IS
PORT(a,b,c,set,clk,scanclk:IN STD_LOGIC; led_out:out std_logic;
ledout:OUT STD_LOGIC_VECTOR(2 DOWNTO 0)); END diancilu;
ARCHITECTURE s OF diancilu IS
SIGNAL cnt,cnm:INTEGER RANGE 0 TO 60; begin
PROCESS(a,b,c) BEGIN
IF(a='1' AND b='0' AND c='0')THEN ledout<=\"001\";
ELSIF(a='0' AND b='1' AND c='0')THEN ledout<=\"010\";
ELSIF(a='0' AND b='0' AND c='1')THEN ledout<=\"100\"; END IF;
END PROCESS; PROCESS(set,clk) BEGIN
IF clk'event AND clk='1'THEN IF set='0' THEN if cnt=59 then cnt<=0; else
cnt<=cnt+1; end if; END IF; END IF;
END PROCESS;
PROCESS(set,scanclk) BEGIN
IF scanclk'event AND scanclk='0' THEN IF set='1' THEN if cnm=59 then cnm<=1; else
cnm<=cnm+1; end if; END IF; END IF;
END PROCESS; process(cnt) begin
IF (cnm<=cnt) THEN led_out<='0'; else led_out<='1'; END IF; end process; END s;
21、设计五位BCD码（8421码）到十六进制数的转换器。结果由共阴极数码管显示。
library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity bcd2hex is
port(shu:in std_logic_vector(4 downto 0); scanclk:in std_logic;
led_out:out std_logic_vector(6 downto 0); scan_out:out std_logic_vector(1 downto 0)); end bcd2hex;
architecture rt1 of bcd2hex is
signal yh,yl :integer range 0 to 15; signal scan:integer range 0 to 1;
signal led:std_logic_vector(6 downto 0); signal y,yy,hex:integer range 0 to 31; begin
yy<=conv_integer(shu);
y<=(yy-0) when yy>=0 and yy<16 else (yy-16) when yy>=16 and yy< else 0; yh<=1 when y>=16 and y<32 else 0;
yl<=(y-0) when y>=0 and y<16 else
(y-16) when y>=16 and y<32 else 0; process(scanclk) begin
if scanclk'event and scanclk='1'then if scan=1 then scan<=0; else
scan<=1; end if; end if;
end process; with scan select hex<=yh when 1, yl when others;
scan_out<=\"10\" when scan=0 else \"01\"; with hex select
led<=\"1111001\" when 1, \"0100100\" when 2, \"0110000\" when 3, \"0011001\" when 4, \"0010010\" when 5, \"0000010\" when 6,
\"1111000\" when 7, \"0000000\" when 8, \"0010000\" when 9, \"0001000\" when 10, \"0000011\" when 11, \"1000110\" when 12, \"1000010\" when 13, \"0000110\" when 14, \"0001110\" when 15, \"1000000\" when 0, \"1000000\" when others; led_out<= not led; end rt1;
22、用结构的描述方法设计一个跑表，计时范围为59.99秒，有计时开始和停止计时控制，复位控制可以对所有计时进行异步复位。计时结果由四位共阴极七段数码管显示。
entity h is
port(rst,en,clk,clk1s:in std_logic;
hex:out std_logic_vector(3 downto 0); ledout:out std_logic_vector(6 downto 0)); end h;
architecture one of h is
signal scan:std_logic_vector(1 downto 0):=\"00\"; signal dout:integer range 0 to 9;
signal led:std_logic_vector(6 downto 0); signal ml:std_logic_vector(3 downto 0); signal mh:std_logic_vector(3 downto 0); signal sl:std_logic_vector(3 downto 0); signal sh:std_logic_vector(3 downto 0); signal ml1,mh1,sl1,sh1:integer range 0 to 9; begin
process(en,rst,clk1s) begin
if rst='1'then
sl<=(others=>'0');sh<=(others=>'0');ml<=(others=>'0');mh<=(others=>'0'); elsif clk1s'event and clk1s='1'then if en='0'then
sl<=sl+'0';sh<=sh+'0';ml<=ml+'0';mh<=mh+'0'; elsif sl<\"1001\" then sl<=sl+'1'; else
sl<=(others=>'0'); if sh<\"1001\"then
sh<=sh+'1';
else sh<=(others=>'0');
if ml<\"1001\" then ml<=ml+'1'; else ml<=(others=>'0');
if mh<\"0101\" then mh<=ml+'1'; else mh<=(others=>'0'); end if; end if; end if; end if; end if; end process;
mh1<=conv_integer(mh); ml1<=conv_integer(ml); sh1<=conv_integer(sh); sl1<=conv_integer(sl); process(clk) begin
if clk'event and clk='1'then if(scan=\"11\")then scan<=\"00\"; else
scan<=scan+'1'; end if; end if; end process; with scan select
dout<=mh1 when \"00\ ml1 when \"01\ sh1 when \"10\ sl1 when \"11\ 0 when others; with scan select
hex<=\"1110\" when \"00\ \"1101\" when \"01\ \"1011\" when \"10\ \"0111\" when \"11\ \"1111\" when others; ledout<=not led; with dout select
led<=\"1111001\"when 1,--1 \"0100100\"when 2,--2 \"0110000\"when 3,--3 \"0011001\"when 4,--4 \"0010010\"when 5,--5
\"0000010\"when 6,--6 \"1111000\"when 7,--7 \"0000000\"when 8,--8 \"0010000\"when 9,--9 \"1000000\"when others;--0 ledout<=not led; end one;
25、血型配对指示器：供血血型和受血血型分别有A、B、AB、O四种。当供血血型和受血血型符合要求时，T指示灯亮，否则F指示灯亮。
library ieee;
use ieee.std_logic_1164.all; entity xuexing1 is
port(a,b:in std_logic_vector(1 downto 0); tout,fout:out std_logic); end xuexing1;
architecture peidui of xuexing1 is begin
process(a,b) begin
if(a=\"00\")then
tout<='0';fout<='1'; -- 00 O型 a：供血 b：受血 elsif(a=\"01\")then if(b=\"01\")then
tout<='0';fout<='1'; -- 01 A型 elsif(b=\"11\")then
tout<='0';fout<='1'; -- 11 AB型 else tout<='1';fout<='0'; end if;
elsif(a=\"10\")then -- 10 B型 if(b=\"10\")then
tout<='0';fout<='1'; elsif(b=\"11\")then
tout<='0';fout<='1'; else tout<='1';fout<='0'; end if; else
if(b=\"11\")then tout<='0';fout<='1'; else
tout<='1';fout<='0'; --低电平亮 end if; end if;
end process; end peidui;
26、可变模计数器，控制信号MA和MB为00、01、10、11时计数器的模分别为3、5、7、9。（计数结果由共阴极七段数码管显示）
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY counter IS
PORT(MA,MB:IN STD_LOGIC; clk:IN STD_LOGIC;
ledout:OUT STD_LOGIC_VECTOR(6 downto 0)); END counter;
ARCHITECTURE a OF counter IS
SIGNAL cnt:STD_LOGIC_VECTOR(3 downto 0); SIGNAL led:STD_LOGIC_VECTOR(6 downto 0); BEGIN
PROCESS(clk) BEGIN
IF(clk'EVENT AND clk='1')THEN IF(MA='0' AND MB='0')THEN IF cnt>=\"0011\"THEN cnt<=\"0001\"; ELSE
cnt<=cnt+'1'; END IF;
ELSIF(MA='0' AND MB='1')THEN IF cnt>=\"0101\"THEN cnt<=\"0001\"; ELSE
cnt<=cnt+'1'; END IF;
ELSIF(MA='1' AND MB='0')THEN IF cnt>=\"0111\"THEN cnt<=\"0001\"; ELSE
cnt<=cnt+'1'; END IF;
ELSIF(MA='1' AND MB='1')THEN IF cnt>=\"1001\"THEN cnt<=\"0001\"; ELSE
cnt<=cnt+'1'; END IF; END IF; END IF; END PROCESS;
ledout<=NOT led; WITH cnt SELECT
led<=\"1111001\" WHEN \"0001\ \"0100100\" WHEN \"0010\ \"0110000\" WHEN \"0011\ \"0011001\" WHEN \"0100\ \"0010010\" WHEN \"0101\ \"0000010\" WHEN \"0110\ \"1111000\" WHEN \"0111\ \"0000000\" WHEN \"1000\ \"0010000\" WHEN \"1001\ \"1000000\" WHEN others; END a;
27、
28、亲子判定器根：据亲子血型关系规则，输当入的亲、子血型符合时，指示灯亮。
library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity qinzijianding is
port(f,m,zi:in std_logic_vector(3 downto 0); en,clr:in std_logic;
start,wrong,y:out std_logic); end qinzijianding;
architecture a of qinzijianding is begin
process begin
start<=en;
if clr='1' or en='0' then
y<='0';start<='0';wrong<='0'; end if;
if(f=\"0001\" and m=\"0001\")then case zi is
when\"0001\"=>y<='1';wrong<='0'; when\"0010\"=>y<='0';wrong<='1'; when\"0100\"=>y<='0';wrong<='1'; when\"1000\"=>y<='0';wrong<='1'; when others=>wrong<='1';y<='0'; end case;
elsif(f=\"0010\" and m=\"0010\")then case zi is
when\"0001\"=>y<='0';wrong<='1';
when\"0010\"=>y<='1';wrong<='0'; when\"0100\"=>y<='1';wrong<='0'; when\"1000\"=>y<='1';wrong<='0'; when others=>wrong<='1';y<='0'; end case;
elsif(f=\"0100\" and m=\"0100\")then case zi is
when\"0001\"=>y<='1';wrong<='0'; when\"0010\"=>y<='0';wrong<='1'; when\"0100\"=>y<='1';wrong<='0'; when\"1000\"=>y<='0';wrong<='1'; when others=>wrong<='1';y<='0'; end case;
elsif(f=\"1000\" and m=\"1000\")then case zi is
when\"0001\"=>y<='1';wrong<='0'; when\"0010\"=>y<='0';wrong<='1'; when\"0100\"=>y<='0';wrong<='1'; when\"1000\"=>y<='1';wrong<='0'; when others=>wrong<='1';y<='0'; end case;
elsif((f=\"0001\" and m=\"0010\")or(f=\"0010\" and m=\"0001\"))then case zi is
when\"0001\"=>y<='0';wrong<='1'; when\"0010\"=>y<='0';wrong<='1'; when\"0100\"=>y<='1';wrong<='0'; when\"1000\"=>y<='1';wrong<='0'; when others=>wrong<='1';y<='0'; end case;
elsif((f=\"0001\" and m=\"1000\")or(f=\"1000\" and m=\"0001\"))then case zi is
when\"0001\"=>y<='1';wrong<='0'; when\"0010\"=>y<='0';wrong<='1'; when\"0100\"=>y<='0';wrong<='1'; when\"1000\"=>y<='1';wrong<='0'; when others=>wrong<='1';y<='0'; end case;
elsif((f=\"0001\" and m=\"0100\")or(f=\"0100\" and m=\"0001\"))then case zi is
when\"0001\"=>y<='1';wrong<='0'; when\"0010\"=>y<='0';wrong<='1'; when\"0100\"=>y<='1';wrong<='0'; when\"1000\"=>y<='0';wrong<='1'; when others=>wrong<='1';y<='0';
end case;
elsif((f=\"1000\" and m=\"0100\")or(f=\"0100\" and m=\"1000\"))then case zi is
when\"0001\"=>y<='0';wrong<='1'; when\"0010\"=>y<='1';wrong<='0'; when\"0100\"=>y<='0';wrong<='1'; when\"1000\"=>y<='0';wrong<='1'; when others=>wrong<='1';y<='0'; end case;
elsif((f=\"1000\" and m=\"0010\")or(f=\"0010\" and m=\"1000\"))then case zi is
when\"0001\"=>y<='0';wrong<='1'; when\"0010\"=>y<='1';wrong<='0'; when\"0100\"=>y<='1';wrong<='0'; when\"1000\"=>y<='1';wrong<='0'; when others=>wrong<='1';y<='0'; end case;
elsif((f=\"0100\" and m=\"0010\")or(f=\"0010\" and m=\"0100\"))then case zi is
when\"0001\"=>y<='0';wrong<='1'; when\"0010\"=>y<='1';wrong<='0'; when\"0100\"=>y<='1';wrong<='0'; when\"1000\"=>y<='1';wrong<='0'; when others=>wrong<='1';y<='0'; end case; end if; end process; end a;
29、模为的计数器，计数步长由控制信号A、B、C进行控制：ABC=001时，步长为1，计数规律为：0-1-2-3-4-5-6-7-8-9-0顺序计数；ABC=010时，步长为3，计数规律为：0-3-6-9-0顺序计数；ABC=110时，步长为1，计数规律为：0-9-8-7-6-5-4-3-2-1-0顺序计数；（计数结果由共阴极七段数码管显示）
library ieee;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY yu IS
port(clk:in std_logic;
din:in std_logic_vector(2 downto 0); ledout:out std_logic_vector(6 downto 0); y:out integer range 0 to 9); end yu;
architecture rtl of yu is
signal cnt:integer range 0 to 9;
SIGNAL led:std_logic_vector(6 downto 0);
begin
Process(clk) begin
if clk'event and clk='1'then if din=\"001\"then if cnt=9 then cnt<=0; else
cnt<=cnt+1; end if;
elsif din=\"010\"then if cnt>6 then cnt<=0; else
cnt<=cnt+3; end if;
elsif din=\"110\"then if cnt=0 then cnt<=9; else
cnt<=cnt-1; end if; end if; end if; y<=cnt; end process;
LEDOUT<=NOT LED; with cnt select
LED<=\"0000110\"when 1, \"1011011\"when 2, \"1001111\"when 3, \"1100110\"when 4, \"1101101\"when 5, \"0000010\"when 6, \"1111000\"when 7, \"0000000\"when 8, \"0010000\"when 9, \"1000000\"when 0,
\"1111101\"when OTHERS; end rtl;
30、模为16的计数器，控制信号为MA和MB。MA和MB为00时不计数，01时加法计数器，10时减法计数器，11时预置数功能。（计数结果由数码管显
示）
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY M16COUNTER IS PORT(
CLK,MA,MB,CLR:IN STD_LOGIC;
YUZHI:IN STD_LOGIC_VECTOR(3 DOWNTO 0); LEDOUT:OUT STD_LOGIC_VECTOR(6 DOWNTO 0) );
END M16COUNTER;
ARCHITECTURE A OF M16COUNTER IS
SIGNAL REG:STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL SET:STD_LOGIC_VECTOR(1 DOWNTO 0); SIGNAL LED:STD_LOGIC_VECTOR(6 DOWNTO 0); BEGIN
SET<=MA&MB; PROCESS(CLK) BEGIN
IF(CLK'EVENT AND CLK='1')THEN IF CLR='1' THEN
REG<=(OTHERS=>'0'); ELSE
IF SET=\"00\"THEN REG<=REG;
ELSIF SET=\"01\"THEN REG<=REG+'1';
ELSIF SET=\"10\"THEN REG<=REG-'1'; ELSE
REG<=YUZHI; END IF; END IF; END IF;
END PROCESS;
LEDOUT<=NOT LED; WITH REG SELECT
LED<=\"1111001\" WHEN \"0001\ \"0100100\" WHEN \"0010\ \"0110000\" WHEN \"0011\ \"0011001\" WHEN \"0100\ \"0010010\" WHEN \"0101\ \"0000010\" WHEN \"0110\ \"1111000\" WHEN \"0111\
\"0000000\" WHEN \"1000\ \"0010000\" WHEN \"1001\ \"0001000\" WHEN \"1010\ \"0000011\" WHEN \"1011\ \"1000110\" WHEN \"1100\ \"0100001\" WHEN \"1101\ \"0000110\" WHEN \"1110\ \"0001110\" WHEN \"1111\ \"1000000\" WHEN OTHERS; END A;
31、8位多功能寄存器：由选择信号和控制信号进行控制。当选择信号S=1时：C=1为加计数器，C=0为减计数器；当选择信号S=0时，将计数值移位输出：C=1时右移串行输出，C=0时左移串行输出。（发光二极管显示）
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY JICUNQI IS PORT(
CLK,S,C,CLR:IN STD_LOGIC;
LED:OUT STD_LOGIC_VECTOR(7 DOWNTO 0) );
END JICUNQI;
ARCHITECTURE A OF JICUNQI IS
SIGNAL REG:STD_LOGIC_VECTOR(7 DOWNTO 0); BEGIN
PROCESS(CLK) BEGIN
IF(CLK'EVENT AND CLK='1')THEN IF CLR='1' THEN
REG<=(OTHERS=>'0'); ELSE
IF S='0'THEN IF C='0' THEN REG<=REG+'1'; ELSE
REG<=REG-'1'; END IF; ELSE
IF C='0' THEN
REG<=REG(6 DOWNTO 0)®(7); ELSE
REG<=REG(0)®(7 DOWNTO 1); END IF; END IF;
END IF; END IF;
END PROCESS; LED<=REG; END A;
32、用状态机设计方法设计一个汽车尾灯控制器。该控制器共有4种状态：状态A代表正常直行或静止；状态B代表左转弯；状态C代表右转弯；状态D代表刹车；三个控制信号：LH左转弯控制；RH右转弯控制；JWH刹车控制。两个输出控制：LD点亮左尾灯控制输出；RD点亮右尾灯控制输出。其状态转移
LH=’1’ RH=’0’ JMH=’0’ LH=’0’ RH=’0’ JMH=’0’ LH=’0’ RH=’1’ JMH=’0’ LD=’1’ RD=’0’ LH=’1’ RH=’0’ JMH=’0’ B A LD=’0’ C LD=’0’ RD=’1’ LH=’0’ RH=’1’ JMH=’0’ LH=’0’ LH=’0’ RD=’0’ RH=’0’ RH=’0’ JMH=’0’ JMH=’0’ LH=’0’ LH=’0’ RH=’0’ RH=’0’ JMH=’1’ JMH=’0’ LD=’1’ RD=’1’ D LH=’0’ RH=’0’ JMH=’1’ 图如下：
ENTITY exam35 IS
PORT (CLK,JMH,LH,RH,RESET: IN std_logic; LD,RD : OUT std_logic); END exam35;
ARCHITECTURE BEHAVIOR OF exam35 IS
TYPE type_sreg IS (right,STOP,TURNL,TURNR); SIGNAL sreg, next_sreg : type_sreg;
BEGIN
PROCESS (sreg,JMH,LH,RH) BEGIN
CASE sreg IS WHEN right =>LD<='0';RD<='0'; IF ( RH='1' AND LH='0' AND JMH='0' ) THEN next_sreg<=TURNR;
END IF;
IF ( LH='1' AND RH='0' AND JMH='0' ) THEN next_sreg<=TURNL; END IF;
IF ( LH='0' AND RH='0' AND JMH='1' ) THEN next_sreg<=STOP; END IF;
IF ( LH='0' AND RH='0' AND JMH='0' ) THEN next_sreg<=right;
END IF;
WHEN STOP =>LD<='1';RD<='1'; IF ( LH='1' ) OR ( RH='1' ) THEN
next_sreg<=STOP; END IF;
IF ( LH='0' AND RH='0' AND JMH='1' ) THEN next_sreg<=STOP;
END IF; IF ( LH='0' AND RH='0' AND JMH='0' ) THEN next_sreg<=right; END IF;
WHEN TURNL =>LD<='1';RD<='0'; IF ( RH='1' ) OR ( JMH='1' ) THEN next_sreg<=TURNL; END IF;
IF ( LH='1' AND RH='0' AND JMH='0' ) THEN next_sreg<=TURNL; END IF;
IF ( LH='0' AND RH='0' AND JMH='0' ) THEN next_sreg<=right; END IF;
WHEN TURNR =>LD<='0';RD<='1';
IF ( LH='1' ) OR ( JMH='1' ) THEN next_sreg<=TURNR; END IF;
IF ( LH='0' AND RH='1' AND JMH='0' ) THEN next_sreg<=TURNR; END IF;
IF ( LH='0' AND RH='0' AND JMH='0' ) THEN next_sreg<=right;
END IF; END CASE;
END PROCESS;
PROCESS (CLK, reset) BEGIN IF ( RESET='1' ) THEN sreg<=STOP; elsif CLK='1' AND CLK'event THEN
sreg <= next_sreg; END IF; END PROCESS; END BEHAVIOR;
33、某医院1到8号病房共8间，每室设有呼叫按钮，同时护士值班室内有一个共阴极的七段数码管显示病房号；当多个病房同时有按钮按下时，病房号小的先显示。
library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity hujiao is
port(input:in std_logic_vector(8 downto 1); ledout:out std_logic_vector(6 downto 0)); end hujiao;
architecture a of hujiao is
signal cnt: std_logic_vector(3 downto 0); signal b:std_logic_vector(6 downto 0);
begin
process(input) begin
if(input(1)='1')then cnt<=\"0001\";
elsif(input(2)='1')then cnt<=\"0010\";
elsif(input(3)='1')then cnt<=\"0011\";
elsif(input(4)='1')then cnt<=\"0100\";
elsif(input(5)='1')then cnt<=\"0101\";
elsif(input(6)='1')then cnt<=\"0110\";
elsif(input(7)='1')then cnt<=\"0111\";
elsif(input(8)='1')then cnt<=\"1000\"; else
cnt<=\"0000\"; end if; end process; with cnt select
b<=\"1111001\"when\"0001\ \"0100100\"when\"0010\ \"0110000\"when\"0011\ \"0011001\"when\"0100\ \"0010010\"when\"0101\ \"0000010\"when\"0110\ \"1111000\"when\"0111\ \"0000000\"when\"1000\ \"1000000\"when others; ledout<=not b; end a;
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