Semiconductor memory device capable of preventing

专利名称：Semiconductor memory device capable of

preventing data of non- selected memorycell from being degraded

发明人：Junichi Miyamoto,Nobuaki

Ohtsuka,Kuniyoshi Yoshikawa,Seiichi Mori

申请号：US07/444998申请日：19891204公开号：US05025417A公开日：19910618

摘要：A semiconductor memory device includes a first power source terminal suppliedwith a first power source voltage for data readout, a second power source terminalsupplied with a second power source voltage for data write-in, memory cells formed of afloating gate type MOS transistor, a voltage switching circuit for selectively outputtingone of the first and second power source voltages supplied to the first and secondpower source terminals, a voltage lowering circuit for lowering the second power sourcevoltage supplied to the second power source terminal and outputting the loweredvoltage, a gate potential control circuit connected to receive an output voltage of thevoltage switching circuit as a power source voltage and supplies an output to the gate ofthe memory cell, and a drain potential control circuit connected to receive an outputvoltage of the voltage lowering circuit as a power source voltage and supplies an outputto the drain of the memory cell. The second power source voltage for data write-insupplied to the second power source terminal is lowered by the power source voltagelowering circuit and is then supplied to the drain of the memory cell via the drain

potential control circuit.

申请人：KABUSHIKI KAISHA TOSHIBA

代理机构：Finnegan, Henderson, Farabow, Garrett and Dunner

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