White Electronic Designs2Mx32 5V Flash Module
FEATURES
WF2M32-XXX5
Access Time of 90, 120, 150ns
• 66 pin, PGA Type, 1.185\" square, Hermetic Ceramic HIP (Package 401).• 68 lead, Hermetic CQFP (G2U), 22.4mm (0.880\") square (Package 510) 3.56mm (0.140\") height. Designed to fi t JEDEC 68 lead 0.990\" CQFJ footprint (FIGURE 3)
Organized as 2Mx32
Commercial, Industrial, and MilitaryTemperature Ranges
5 Volt Read and Write. 5V ± 10% Supply.
Data# Polling and Toggle Bit feature for detection of program or erase cycle completion.
Supports reading or programming data to a sector not being erased.
RESET# pin resets internal state machine to the read mode.
Built in Decoupling Caps and Multiple Ground Pins for Low Noise Operation, Separate Power and Ground Planes to improve noise immunity
Packaging:
Low Power CMOS
Sector Architecture
• 32 equal size sectors of 64KBytes per each 2Mx8
chip• Any combination of sectors can be erased. Also supports full chip erase.
Minimum 100,000 Write/Erase Cycles Minimum
* This product is subject to change without notice.
Note: For programming information refer to Flash Programming 16M5 Application Note.
FIGURE 1 – PIN CONFIGURATION FOR WF2M32-XHX5Top View1 12 23 34 45 56I/O8I/O9I/O10A14A16A11A0A18I/O0I/O1I/O2WE2#CS2#GNDI/O11A10A9A15VCCCS1#A19I/O3I/O15I/O14I/O13I/O12OE#A17WE1#I/O7I/O6I/O5I/O4I/O24I/O25I/O26A7A12A20A13A8I/O16I/O17I/O18VCCCS4#WE4#I/O27A4A5A6WE3#CS3#GNDI/O19I/O31I/O30I/O29I/O28A1A2A3I/O23I/O22I/O21I/O208888Pin DescriptionI/O0-31A0-20WE1-4#CS1-4#OE#VCCGNDData Inputs/OutputsAddress InputsWrite EnablesChip SelectsOutput EnablePower SupplyGroundBlock DiagramWE1# CS1#WE2# CS2#WE3# CS3#WE4# CS4#OE#A0-202M x 82M x 82M x 82M x 8I/O0-7I/O8-15I/O16-23I/O24-3111 22 33 44 55 66RESET# internally tied to VCC in the HIP package for this pin con-fi guration. See Alternate Pin Confi guration with RESET# tied to pin 12 for system control of reset (FIGURE 10, page 11).October 2004Rev. 5
1White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
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White Electronic DesignsWF2M32-XXX5
FIGURE 2 – PIN CONFIGURATION FOR WF2M32-XG2UX5
Top ViewRESET#A0A1A2A3A4A5CS3#GNDCS4#WE1#A6A7A8A9A10VCCPin DescriptionI/O0-31A0-20WE1-4#CS1-4#OE#VCCGNDRESET#Data Inputs/OutputsAddress InputsWrite EnablesChip SelectsOutput EnablePower SupplyGroundReset9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61I/O0I/O1I/O2I/O3I/O4I/O5I/O6I/O7GNDI/O8I/O9I/O10I/O11I/O12I/O13I/O14I/O151011121314151617181920212223242526605958575655545352515049484746454427 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43I/O16I/O17I/O18I/O19I/O20I/O21I/O22I/O23GNDI/O24I/O25I/O26I/O27I/O28I/O29I/O30I/O31Block DiagramWE1# CS1#RESET#OE#A0-202M x 82M x 82M x 82M x 8WE2# CS2#WE3# CS3#WE4# CS4#VCCA11A12A13A14A15A16CS1#OE#CS2#A17WE2#WE3#WE4#A18A19A208888I/O0-7I/O8-15I/O16-23I/O24-31The WEDC 68 lead G2U CQFP fi lls the same fi t and function as the JEDEC 68 lead CQFJ or 68 PLCC. But the G2U has the TCE and lead inspection advantage of the CQFP form.0.940\"October 2004Rev. 5
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White Electronic DesignsABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on Any Pin Relative to VSS Power DissipationStorage TemperatureShort Circuit Output CurrentEndurance – Write/Erase Cycles (Extended Temp)Data Retention
SymbolVT PTTstgIOS
Ratings-2.0 to +7.0
8-65 to +125100100,000 min
20
UnitVW°CmAcyclesyears
WF2M32-XXX5
CAPACITANCE
TA = +25°C, f = 1.0MHz
Parameter
OE# capacitance WE1-4# capacitance HIP (PGA)H IP (Alternate pinout) CQFP G4T CQFP G2U
G2U (Alternate pinout)CS1-4# capacitance Data I/O capacitanceAddress input capacitance
SymbolCOECWECWECWECWECWECCSCI/OCAD
Max5020505020502020 50
UnitpFpFpFpFpFpFpFpFpF
This parameter is guaranteed by design but not tested.
RECOMMENDED DC OPERATING CONDITIONS
ParameterSupply VoltageGroundInput High VoltageInput Low VoltageOperating Temperature (Mil.)Operating Temperature (Ind.)
SymbolMinVCCVSSVIHVILTATA
4.502.0-0.5-55-40
Typ5.00----Max5.50VCC + 0.5+0.8+125+85
UnitVVVV°C°C
DC CHARACTERISTICS – CMOS COMPATIBLE
VCC = 5.0V, VSS = 0V, -55°C ≤ TA ≤ +125°C
Parameter
Input Leakage CurrentOutput Leakage Current
VCC Active Current for Read (1)
VCC Active Current for Program or Erase (2) VCC Standby Current Output Low VoltageOutput High Voltage
Low VCC Lock-Out Voltage
SymbolILIILOx32ICC1ICC2ICC3VOLVOHVLKO
Conditions
VCC = 5.5, VIN = GND to VCCVCC = 5.5, VIN = GND to VCCCS# = VIL, OE# = VIH, f = 5MHzCS# = VIL, OE# = VIH
VCC = 5.5, CS# = VIH, f = 5MHz, RESET# = VCC ± 0.3VIOL = 12.0 mA, VCC = 4.5IOH = -2.5 mA, VCC = 4.5
Min
Max10101602408.00.454.2
UnitµAµAmAmAmAVVV
0.85xVCC
3.2
NOTES:1. The ICC current listed includes both the DC operating current and the frequency
dependent component (@ 5MHz). The frequency component typically is less than 2mA/MHz, with OE# at VIH.
2. ICC active while Embedded Algorithm (program or erase) is in progress.3. DC test conditions VIL = 0.3V, VIH = VCC - 0.3V
October 2004Rev. 5
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White Electronic DesignsVCC = 5.0V, -55°C ≤ TA ≤ +125°C
Parameter
Write Cycle Time
Chip Select Setup TimeWrite Enable Pulse WidthAddress Setup TimeData Setup TimeData Hold TimeAddress Hold Time
Write Enable Pulse Width High
Duration of Byte Programming Operation (1)Sector Erase (2)
Read Recovery Time before WriteVCC Setup Time
Chip Programming TimeChip Erase Time (3)
Output Enable Hold Time (4) RESET# Pulse Width (5)
SymboltAVAVtELWLtWLWHtAVWLtDVWHtWHDXtWLAXtWHWLtWHWH1tWHWH2tGHWLtVCS
tWCtCStWPtAStDStDHtAHtWPH
Min9004504504520
-90
Max
Min12005005005020
-120
Max
WF2M32-XXX5
AC CHARACTERISTICS – WRITE/ERASE/PROGRAM OPERATIONS - WE# CONTROLLED
Min15005005005020
-150
Max
Unitnsnsnsnsnsnsnsnsµssecµsµssecsecnsns
30015
050
44256
tOEHtRP
10500
10500050
30015
050
44256
10500
30015
44256
NOTES:
1. Typical value for tWHWH1 is 7µs.2. Typical value for tWHWH2 is 1sec.
3. Typical value for Chip Erase Time is 32sec.4. For Toggle and Data Polling.
5. RESET# internally tied to VCC for the default pin confi guration in the HIP package.
AC CHARACTERISTICS – READ-ONLY OPERATIONS
VCC = 5.0V, -55°C ≤ TA ≤ +125°C
Parameter
Read Cycle TimeAddress Access TimeChip Select Access TimeOutput Enable to Output Valid
Chip Select High to Output High Z (1)Output Enable High to Output High Z (1)Output Hold from Addresses, CS# or OE# Change, whichever is FirstRST Low to Read Mode (1,2)
SymboltAVAVtAVQVtELQVtGLQVtEHQZtGHQZtAXQX
tRCtACCtCEtOEtDFtDFtOHtReady
Min90
-90
Max9090402020
0
20
0
20
Min120
-120
Max120120503030
0
20
Min150
-150
Max150150553535
Unitnsnsnsnsnsnsnsµs
NOTES:
1. Guaranteed by design, not tested.
2. RESET# internally tied to VCC for the default pin confi guration in the HIP package.
October 2004Rev. 5
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White Electronic DesignsVCC = 5.0V, VSS = 0V, -55°C ≤ TA ≤ +125°C
Parameter
Write Cycle Time
Write Enable Setup TimeChip Select Pulse WidthAddress Setup TimeData Setup TimeData Hold TimeAddress Hold Time
Chip Select Pulse Width High
Duration of Byte Programming Operation (1)Sector Erase Time (2)Read Recovery TimeChip Programming TimeChip Erase Time (3)
Output Enable Hold Time (4)
NOTES:
1. Typical value for tWHWH1 is 7µs.2. Typical value for tWHWH2 is 1sec.
3. Typical value for Chip Erase Time is 32sec.4. For Toggle and Data Polling.
WF2M32-XXX5
AC CHARACTERISTICS – WRITE/ERASE/PROGRAM OPERATIONS,CS# CONTROLLED
SymboltAVAVtWLELtELEHtAVELtDVEHtEHDXtELAXtEHELtWHWH1tWHWH2tGHEL
tWCtWStCPtAStDStDHtAHtCPH
-90-120MinMaxMinMax9012000455000455000455020 203003001515
00
4444256256
1010
Min
15005005005020
-150
Max
Unitnsnsnsnsnsnsnsnsµssecµssecsecns
30015
0
44256
10
tOEH
FIGURE 3 – AC TEST CIRCUIT
AC TEST CONDITIONSIOLCurrent SourceParameterInput Pulse LevelsInput Rise and FallInput and Output Reference LevelOutput Timing Reference Level TypVIL = 0, VIH = 3.051.51.5UnitVnsVVD.U.T.Ceff = 50 pfVZ ≈ 1.5V(Bipolar Supply)IOHCurrent SourceNotes:VZ is programmable from -2V to +7V.IOL & IOH programmable from 0 to 16mA.Tester Impedance Z0 = 75 ý.VZ is typically the midpoint of VOH and VOL.IOL & IOH are adjusted to simulate a typical resistive load circuit.ATE tester includes jig capacitance.FIGURE 4 – RESET TIMING DIAGRAM
RESET#tRPtReadyOctober 2004Rev. 5
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White Electronic DesignsWF2M32-XXX5
FIGURE 5 – AC WAVEFORMS FOR READ OPERATIONS
OE#October 2004Rev. 5
6
WE#White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
CS#元器件交易网www.cecb2b.com
White Electronic DesignsWF2M32-XXX5
FIGURE 6 – WRITE/ERASE/PROGRAM OPERATION, WE# CONTROLLED
Data# PollingOE#CS#NOTES:1. PA is the address of the memory location to be programmed.2. PD is the data to be programmed at byte address.3. D7# is the output of the complement of the data written to each chip.4. DOUT is the output of the data written to the device.5. Figure indicates last two bus cycles of four bus cycle sequence.October 2004Rev. 5
7
WE#White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
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White Electronic DesignsWF2M32-XXX5
FIGURE 7 – AC WAVEFORMS CHIP/SECTOR ERASE OPERATIONS
OE#NOTE: 1. SA is the sector address for Sector Erase.October 2004Rev. 5
8
WE#CS#White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
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White Electronic DesignsWF2M32-XXX5
FIGURE 8 – AC WAVEFORMS FOR DATA# POLLING DURING EMBEDDED ALGORITHM
OPERATIONS
tDFtOHHigh ZD7 = Valid DatatCHtOEHtCEtWHWH 1 or 2DataWhite Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
tOEOE#October 2004Rev. 5
WE#CS#9
D0-D6D7D0-D6 = InvalidD7#D0-D7Valid Data元器件交易网www.cecb2b.com
White Electronic DesignsWF2M32-XXX5
FIGURE 9 – ALTERNATE CS# CONTROLLED PROGRAMMING OPERATION TIMINGS
Data# PollingtGHELtCPOE#Notes:1. PA represents the address of the memory location to be programmed.2. PD represents the data to be programmed at byte address.3. D7# is the output of the complement of the data written to each chip.4. DOUT is the output of the data written to the device.5. Figure indicates the last two bus cycles of a four bus cycle sequence.October 2004Rev. 5
10
WE#CS#tWStCPHWhite Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
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White Electronic DesignsWF2M32-XXX5
FIGURE 10 – ALTERNATE PIN CONFIGURATION FOR WF2M32I-XHX5
TOP VIEW1 12 23 34 45 56I/O8I/O9I/O10A14A16A11A0A18I/O0I/O1I/O2RESET#CS2#GNDI/O11A10A9A15VCCCS1#A19I/O3I/O15I/O14I/O13I/O12OE#A17WE#I/O7I/O6I/O5I/O4I/O24I/O25I/O26A7A12NCA13A8I/O16I/O17I/O18VCCCS4#NCI/O27A4A5A6A20CS3#GNDI/O19I/O31I/O30I/O29I/O28A1A2A3I/O23I/O222M x 82M x 82M x 82M x 8RESET#WE#OE#A0-20PIN DESCRIPTIONI/O0-31A0-20WE#CS1-4#OE#VCCGNDRESET#Data Inputs/OutputsAddress InputsWrite EnableChip SelectsOutput EnablePower SupplyGroundResetBLOCK DIAGRAMCS1#CS2#CS3#CS4#I/O21I/O20888811 22 33 44 55 66I/O0-7I/O8-15I/O16-23I/O24-31FIGURE 11 – ALTERNATE PIN CONFIGURATION FOR WF2M32U-XG2UX5
TOP VIEWRESET#A0A1A2A3A4A5NCGNDNCWE#A6A7A8A9A10VCCPIN DESCRIPTIONI/O0-31A0-20WE#CS#OE#VCCGNDRESET#Data Inputs/OutputsAddress InputsWrite EnableChip SelectOutput EnablePower SupplyGroundReset9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61I/O0I/O1I/O2I/O3I/O4I/O5I/O6I/O7GNDI/O8I/O9I/O10I/O11I/O12I/O13I/O14I/O151011121314151617181920212223242526605958575655545352515049484746454427 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43I/O16I/O17I/O18I/O19I/O20I/O21I/O22I/O23GNDI/O24I/O25I/O26I/O27I/O28I/O29I/O30I/O310.940\"The WEDC 68 lead G2U CQFP fi lls the same fi t and function as the JEDEC 68 lead CQFJ or 68 PLCC. But the G2U has the TCE and lead inspection advantage of the CQFP form.BLOCK DIAGRAMRESET# CS# WE#OE#A0-202M x 82M x 82M x 82M x 8VCCA11A12A13A14A15A16CS#OE#NCA17NCNCNCA18A19A208888I/O0-7I/O8-15I/O16-23I/O24-31October 2004Rev. 5
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White Electronic DesignsWF2M32-XXX5
FIGURE 12 – PIN CONFIGURATION FOR WF2M32I-XG2UX5
TOP VIEWRESET#A0A1A2A3A4A5CS3#GNDCS4#WE#A6A7A8A9A10VCCPIN DESCRIPTIONI/O0-31A0-20WE#CS1-4#OE#VCCGNDRESET#Data Inputs/OutputsAddress InputsWrite EnableChip SelectsOutput EnablePower SupplyGroundReset9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61I/O0I/O1I/O2I/O3I/O4I/O5I/O6I/O7GNDI/O8I/O9I/O10I/O11I/O12I/O13I/O14I/O151011121314151617181920212223242526605958575655545352515049484746454427 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43I/O16I/O17I/O18I/O19I/O20I/O21I/O22I/O23GNDI/O24I/O25I/O26I/O27I/O28I/O29I/O30I/O31BLOCK DIAGRAMCS1#RESET#WE#OE#A0-202M x 82M x 8CS2#CS3#CS4#2M x 82M x 8VCCA11A12A13A14A15A16CS1#OE#CS2#A17NCNCNCA18A19A208888I/O0-7I/O8-15I/O16-23I/O24-31The WEDC 68 lead G2U CQFP fi lls the same fi t and function as the JEDEC 68 lead CQFJ or 68 PLCC. But the G2U has the TCE and lead inspection advantage of the CQFP form.0.940\"October 2004Rev. 5
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White Electronic DesignsWF2M32-XXX5
PACKAGE 401: 66 PIN, PGA TYPE, CERAMIC HEX-IN-LINE PACKAGE, HIP (H)
30.1 (1.185) ± 0.38 (0.015) SQPIN 1 IDENTIFIERSQUARE PADON BOTTOM25.4 (1.0) TYP6.22 (0.245)MAX3.81 (0.150)±0.1 (0.005)2.54 (0.100)TYP1.27 (0.050) ± 0.1 (0.005)0.76 (0.030) ± 0.1 (0.005)15.24 (0.600) TYP1.27 (0.050) TYP DIA0.46 (0.018) ± 0.05 (0.002) DIA25.4 (1.0) TYPALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
October 2004Rev. 5
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White Electronic DesignsWF2M32-XXX5
PACKAGE 510: 68 LEAD, CERAMIC QUAD FLAT PACK, CQFP (G2U)
The WEDC 68 lead G2U CQFP fi lls the same fi t and function as the JEDEC 68 lead CQFJ or 68 PLCC. But the G2U has the TCE and lead inspection advantage of the CQFP form.0.940\"TYPALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
October 2004Rev. 5
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I
I
White Electronic DesignsN
WF2M32-XXX5
ORDERING INFORMATION
W F 2M32 X - XXX X X 5 X
LEAD FINISH:
Blank = Gold plated leadsA = Solder dip leads
VPP PROGRAMMING VOLTAGE 5 = 5 V
DEVICE GRADE:
Q = Compliant -55°C to +125°C M = Military -55°C to +125°C I = Industrial -40°C to +85°C C = Commercial 0°C to +70°C PACKAGE TYPE: H = Ceramic Hex In line Package, HIP (Package 401) G2U = 22.4mm Ceramic Quad Flat Pack, CQFP (Package 510) ACCESS TIME (ns) IMPROVEMET MARK • For HIP Package Blank = 4CS# and 4WE#
= 4CS# and 1WE#, RESET# • For G2U Package Blank = 4CS# and 4WE#
U = 1CS# and 1WE#
= 4CS# and 1WE#, RESET#
ORGANIZATION, 2M x 32
User confi gurable as 4M x 16 or 8M x 8
(Except WF2M32U-XG2UX which is 32 bit wide only.)
Flash WHITE ELECTRONIC DESIGNS CORP.
October 2004Rev. 5
15White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
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