专利名称：Method and apparatus for bus arbitration in
a multiple bus information handling systemusing time slot assignment values
发明人：Wan L. Leung申请号：US08/287213申请日：19940808公开号：US05598542A公开日：19970128
摘要：In a computer system having a central processing unit (CPU) in circuit
communication with a memory via a memory bus and having first and second peripheralbus controllers generating first and second dissimilar peripheral buses, a multibus arbiteris provided for arbitrating access of a memory bus between the two dissimilar buses. Themultibus arbiter has an assignment register, a time slot pointer, and an arbitration circuit.The length of the assignment register and time slot pointer controls the granularity ofcontrol of accesses to the memory bus by the peripheral buses. The assignment registerholds a multibit assignment value that determines which of the two peripheral buses willbe given access to the memory bus for a given time slot during contention. The time slotpointer selects one of the bits of the assignment register and points to a different bitresponsive to both peripheral buses requesting access to the memory bus at the sametime and one of said peripheral bus arbiters indicating that the current access of thememory bus is complete.
申请人：INTERNATIONAL BUSINESS MACHINES CORPORATION
代理人：George E. Grosser
更多信息请下载全文后查看
因篇幅问题不能全部显示，请点此查看更多更全内容