Method for manufacturing semiconductor integrated

专利名称：Method for manufacturing semiconductor

integrated circuit device

发明人：Tsuyoshi Fujiwara,Katsuyuki Asaka,Yasuhiro

Nariyoshi,Yoshinori Hoshino,KazutoshiOomori

申请号：US10930845申请日：20040901公开号：US07084055B2公开日：20060801

专利附图：

摘要：It is desirable to prevent breakage and separation of wiring of a semiconductor

integrated circuit device, such as a bit-line of a DRAM. To accomplish this, disclosed is amethod in which, e.g., a high density plasma silicon oxide film is deposited on wirings (e.g.,a bit-line that is connected to the source and drain region of a memory cell selectionMISFET of a DRAM memory cell) by means of a high density plasma CVD technique, at afirst temperature, and the structure is subjected to RTA (heat treatment) at a secondtemperature higher than the first temperature (e.g., 750° C.). Via holes are then formed inthe high density plasma silicon oxide film, and first and second conductive films are thenformed, the first conductive film being formed in the via holes and at a third temperaturelower than the first temperature. The first and second conductive layers are thenpolished to remain selectively within the via holes. In heat treating the high densityplasma silicon oxide film, the temperature is raised from the first temperature to thesecond temperature at a maximum speed of 60° C./second or less.

申请人：Tsuyoshi Fujiwara,Katsuyuki Asaka,Yasuhiro Nariyoshi,YoshinoriHoshino,Kazutoshi Oomori

地址：Hamura JP,Ome JP,Kodaira JP,Tamamura JP,Ome JP

国籍：JP,JP,JP,JP,JP

代理机构：Antonelli, Terry, Stout and Kraus, LLP.

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