MAX 3000A
®Programmable Logic
Device Family
Data Sheet
June 2002, ver. 3.0
Features...
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High–performance, low–cost CMOS EEPROM–based programmable logic devices (PLDs) built on a MAX® architecture (see Table1)3.3-V in-system programmability (ISP) through the built–in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with advanced pin-locking capability–ISP circuitry compliant with IEEE Std. 1532
Built–in boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990Enhanced ISP features:–Enhanced ISP algorithm for faster programming–ISP_Done bit to ensure complete programming–Pull-up resistor on I/O pins during in–system programmingHigh–density PLDs ranging from 600 to 10,000 usable gates 4.5–ns pin–to–pin logic delays with counter frequencies of up to 227.3MHz
MultiVoltTM I/O interface enabling the device core to run at 3.3 V, while I/O pins are compatible with 5.0–V, 3.3–V, and 2.5–V logic levels
Pin counts ranging from 44 to 256 in a variety of thin quad flat pack (TQFP), plastic quad flat pack (PQFP), plastic J–lead chip carrier (PLCC), and FineLine BGATM packagesHot–socketing support
Programmable interconnect array (PIA) continuous routing structure for fast, predictable performance
Table 1.MAX3000A Device Features
Feature
Usable gatesMacrocellsLogic array blocksMaximum user I/O pinstPD (ns)tSU (ns)tCO1 (ns)fCNT (MHz)
EPM3032A
600322344.52.93.0227.3
EPM3064A
1,250644664.52.83.1222.2
EPM3128A
2,5001288965.03.33.4192.3
EPM3256A
5,000256161585.53.93.5172.4
EPM3512A
10,000512322087.55.64.7116.3
Altera Corporation
DS-M3000A-3.0
1
MAX 3000A Programmable Logic Device Family Data Sheet
...and More Features
General Description
2■PCI compatible
■Bus–friendly architecture including programmable slew–rate control■Open–drain output option
■Programmable macrocell flipflops with individual clear, preset, clock, and clock enable controls
■Programmable power–saving mode for a power reduction of over 50% in each macrocell
■Configurable expander product–term distribution, allowing up to 32 product terms per macrocell
■Programmable security bit for protection of proprietary designs■
Enhanced architectural features, including:–6 or 10 pin– or logic–driven output enable signals–Two global clock signals with optional inversion–Enhanced interconnect resources for improved routability–Programmable output slew–rate control
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Software design support and automatic place–and–route provided by Altera’s development systems for Windows–based PCs and Sun SPARCstations, and HP 9000 Series 700/800 workstations
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Additional design entry and simulation support provided by EDIF 2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM), Verilog HDL, VHDL, and other interfaces to popular EDA tools from third–party manufacturers such as Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, Synplicity, and VeriBest
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Programming support with the Altera master programming unit (MPU), MasterBlasterTM communications cable, ByteBlasterMVTM parallel port download cable, BitBlasterTM serial download cable as well as programming hardware from third–party manufacturers and any in–circuit tester that supports JamTM Standard Test and
Programming Language (STAPL) Files (.jam), Jam STAPL Byte-Code Files (.jbc), or Serial Vector Format Files (.svf)
MAX3000A devices are low–cost, high–performance devices based on the Altera MAX architecture. Fabricated with advanced CMOS technology, the EEPROM–based MAX3000A devices operate with a 3.3-V supply voltage and provide 600 to 10,000 usable gates, ISP, pin-to-pin delays as fast as 4.5 ns, and counter speeds of up to 227.3MHz. MAX3000A devices in the –4, –5, –6, –7, and –10 speed grades are compatible with the timing requirements of the PCI Special Interest Group (PCI SIG) PCILocal Bus Specification, Revision2.2. See Table2.
Altera Corporation
Altera CorporationMAX 3000A Programmable Logic Device Family Data Sheet
Table 2.MAX3000A Speed GradesDevice
Speed Grade
–4
–5
–6
–7–10EPM3032AvvvEPM3064Av
v
vEPM3128Av
vvEPM3256AvvEPM3512A
v
v
The MAX3000A architecture supports 100% transistor-to-transistor logic (TTL) emulation and high–density small-scale integration (SSI),
medium-scale integration (MSI), and large-scale integration (LSI) logic functions. The MAX3000A architecture easily integrates multiple devices ranging from PALs, GALs, and 22V10s to MACH and pLSI devices.
MAX3000A devices are available in a wide range of packages, including PLCC, PQFP, and TQFP packages. See Table3.Table 3.MAX3000A Maximum User I/O PinsNote (1)
Device
44–Pin 44–Pin 100–Pin144–Pin 208–Pin 256-Pin PLCC
TQFPTQFPTQFPPQFPFineLine
BGA
EPM3032A3434EPM3064A34
34
66EPM3128A80
96EPM3256A116
158EPM3512A172
208
Note:(1)
When the IEEE Std. 1149.1 (JTAG) interface is used for in–system programming or boundary–scan testing, four I/O pins become JTAG pins.
MAX3000A devices use CMOS EEPROM cells to implement logic
functions. The user–configurable MAX3000A architecture accommodates a variety of independent combinatorial and sequential logic functions. The devices can be reprogrammed for quick and efficient iterations during design development and debugging cycles, and can be programmed and erased up to 100 times.
3
MAX 3000A Programmable Logic Device Family Data Sheet
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Functional Description
4MAX3000A devices contain 32 to 512 macrocells, combined into groups of 16 macrocells called logic array blocks (LABs). Each macrocell has a programmable–AND/fixed–OR array and a configurable register with independently programmable clock, clock enable, clear, and preset functions. To build complex logic functions, each macrocell can be supplemented with shareable expander and high–speed parallel
expander product terms to provide up to 32 product terms per macrocell.MAX3000A devices provide programmable speed/power optimization. Speed–critical portions of a design can run at high speed/full power, while the remaining portions run at reduced speed/low power. This speed/power optimization feature enables the designer to configure one or more macrocells to operate at 50% or lower power while adding only a nominal timing delay. MAX3000A devices also provide an option that reduces the slew rate of the output buffers, minimizing noise transients when non–speed–critical signals are switching. The output drivers of all MAX3000A devices can be set for 2.5V or 3.3V, and all input pins are 2.5–V, 3.3–V, and 5.0-V tolerant, allowing MAX3000A devices to be used in mixed–voltage systems.
MAX3000A devices are supported by Altera development systems, which are integrated packages that offer schematic, text—including VHDL, Verilog HDL, and the Altera Hardware Description Language (AHDL)—and waveform design entry, compilation and logic synthesis, simulation and timing analysis, and device programming. The software provides EDIF 2 0 0 and 3 0 0, LPM, VHDL, Verilog HDL, and other
interfaces for additional design entry and simulation support from other industry–standard PC– and UNIX–workstation–based EDA tools. The software runs on Windows–based PCs, as well as Sun SPARCstation, and HP 9000 Series 700/800 workstations.
For more information on development tools, see the MAX+PLUSII Programmable Logic Development System & Software Data Sheet andthe Quartus Programmable Logic Development System & Software Data Sheet.The MAX3000A architecture includes the following elements:
■Logic array blocks (LABs)■Macrocells
■Expander product terms (shareable and parallel)■Programmable interconnect array (PIA)■
I/O control blocks
The MAX3000A architecture includes four dedicated inputs that can be used as general–purpose inputs or as high–speed, global control signals (clock, clear, and two output enable signals) for each macrocell and I/O pin. Figure1 shows the architecture of MAX3000A devices.
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MAX 3000A Programmable Logic Device Family Data Sheet
Figure 1. MAX3000A Device Block Diagram
INPUT/GCLK1INPUT/OE2/GCLK2INPUT/OE1INPUT/GCLRn6 or 10 Output Enables (1) LAB AI/OControlBlock2 to16Macrocells1 to 1636366 or 10 Output Enables (1) LAB BMacrocells17 to 322 to16I/OControlBlock2 to 16 I/O2 to 16 I/O166 or 10LAB CI/OControlBlock2 to16Macrocells33 to 48362 to 16PIA162 to 16LAB D36Macrocells49 to 642 to16I/OControlBlock6 or 102 to 16 I/O2 to 16 I/O166 or 102 to 16162 to 166 or 10Note:(1)
EPM3032A, EPM3064A, EPM3128A, and EPM3256A devices have six output enables. EPM3512A devices have 10output enables.
Logic Array Blocks
The MAX3000A device architecture is based on the linking of
high–performance LABs. LABs consist of 16–macrocell arrays, as shown in Figure1. Multiple LABs are linked together via the PIA, a global bus that is fed by all dedicated input pins, I/O pins, and macrocells. Each LAB is fed by the following signals:
■■
36 signals from the PIA that are used for general logic inputsGlobal controls that are used for secondary register functions
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MAX 3000A Programmable Logic Device Family Data Sheet
Macrocells
MAX3000A macrocells can be individually configured for either
sequential or combinatorial logic operation. Macrocells consist of three functional blocks: logic array, product–term select matrix, and programmable register. Figure2 shows a MAX3000A macrocell.
Figure 2. MAX3000A Macrocell
LAB Local ArrayParallel LogicExpanders(from othermacrocells)Global ClearGlobal Clocks2ProgrammableRegisterRegisterBypassTo I/OControlBlockPRND/TQProduct-TermSelectMatrixVCCClock/ Enable SelectENACLRNClear SelectShared LogicExpanders36 Signalsfrom PIA16 ExpanderProduct TermsTo PIACombinatorial logic is implemented in the logic array, which provides five product terms per macrocell. The product–term select matrix
allocates these product terms for use as either primary logic inputs (to the OR and XOR gates) to implement combinatorial functions, or as secondary inputs to the macrocell’s register preset, clock, and clock enable control functions.
Two kinds of expander product terms (“expanders”) are available to supplement macrocell logic resources:
■■
Shareable expanders, which are inverted product terms that are fed back into the logic array
Parallel expanders, which are product terms borrowed from adjacent macrocells
The Altera development system automatically optimizes product–term allocation according to the logic requirements of the design.
6
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Altera CorporationMAX 3000A Programmable Logic Device Family Data Sheet
For registered functions, each macrocell flipflop can be individually
programmed to implement D, T, JK, or SR operation with programmable clock control. The flipflop can be bypassed for combinatorial operation. During design entry, the designer specifies the desired flipflop type; the Altera development system software then selects the most efficient flipflop operation for each registered function to optimize resource utilization.
Each programmable register can be clocked in three different modes:
■Global clock signal mode, which achieves the fastest clock–to–output performance.
■
Global clock signal enabled by an active–high clock enable. A clock enable is generated by a product term. This mode provides an enable on each flipflop while still achieving the fast clock–to–output performance of the global clock.
■
Array clock implemented with a product term. In this mode, the flipflop can be clocked by signals from buried macrocells or I/O pins.
Two global clock signals are available in MAX3000A devices. As shown in Figure1, these global clock signals can be the true or the complement of either of the two global clock pins, GCLK1 or GCLK2.
Each register also supports asynchronous preset and clear functions. As shown in Figure2, the product–term select matrix allocates product terms to control these operations. Although the product–term–driven preset and clear from the register are active high, active–low control can be obtained by inverting the signal within the logic array. In addition, each register clear function can be individually driven by the active–low dedicated global clear pin (GCLRn).
Expander Product Terms
Although most logic functions can be implemented with the five product terms available in each macrocell, highly complex logic functions require additional product terms. Another macrocell can be used to supply the required logic resources. However, the MAX3000A architecture also offers both shareable and parallel expander product terms (“expanders”) that provide additional product terms directly to any macrocell in the same LAB. These expanders help ensure that logic is synthesized with the fewest possible logic resources to obtain the fastest possible speed.
7
MAX 3000A Programmable Logic Device Family Data Sheet
8Shareable Expanders
Each LAB has 16 shareable expanders that can be viewed as a pool of uncommitted single product terms (one from each macrocell) with inverted outputs that feed back into the logic array. Each shareable
expander can be used and shared by any or all macrocells in the LAB to build complex logic functions. Shareable expanders incur a small delay (tSEXP). Figure3 shows how shareable expanders can feed multiple macrocells.
Figure 3. MAX3000A Shareable Expanders
Shareable expanders can be shared by any or all macrocells in an LAB.
MacrocellProduct-TermLogicProduct-Term Select MatrixMacrocellProduct-TermLogic36 Signals16 Sharedfrom PIAExpanders
Parallel Expanders
Parallel expanders are unused product terms that can be allocated to a neighboring macrocell to implement fast, complex logic functions. Parallel expanders allow up to 20 product terms to directly feed the
macrocell OR logic, with five product terms provided by the macrocell and 15 parallel expanders provided by neighboring macrocells in the LAB.
Altera Corporation
MAX 3000A Programmable Logic Device Family Data Sheet
The Altera development system compiler can automatically allocate up to three sets of up to five parallel expanders to the macrocells that require additional product terms. Each set of five parallel expanders incurs a small, incremental timing delay (tPEXP). For example, if a macrocell requires 14product terms, the compiler uses the five dedicated product terms within the macrocell and allocates two sets of parallel expanders; the first set includes five product terms, and the second set includes four product terms, increasing the total delay by 2 × tPEXP.
Two groups of eight macrocells within each LAB (e.g., macrocells 1 through 8 and 9through 16) form two chains to lend or borrow parallel expanders. A macrocell borrows parallel expanders from lower–numbered macrocells. For example, macrocell 8 can borrow parallel
expanders from macrocell 7, from macrocells 7 and 6, or from macrocells 7, 6, and 5. Within each group of eight, the lowest–numbered macrocell can only lend parallel expanders and the highest–numbered macrocell can only borrow them. Figure4 shows how parallel expanders can be borrowed from a neighboring macrocell.
Figure 4. MAX3000A Parallel Expanders
Unused product terms in a macrocell can be allocated to a neighboring macrocell.
FromPreviousMacrocellPresetProduct-erSelectMatrixClockClearMacrocellProduct-Term LogicPresetProduct-TermSelectMatrixMacrocellProduct-Term LogicClockClear36 Signalsfrom PIA16 SharedExpandersTo NextMacrocellAltera Corporation 9
MAX 3000A Programmable Logic Device Family Data Sheet
10Programmable Interconnect Array
Logic is routed between LABs on the PIA. This global bus is a
programmable path that connects any signal source to any destination on the device. All MAX3000A dedicated inputs, I/O pins, and macrocell outputs feed the PIA, which makes the signals available throughout the entire device. Only the signals required by each LAB are actually routed from the PIA into the LAB. Figure5 shows how the PIA signals are routed into the LAB. An EEPROM cell controls one input to a two-input AND gate, which selects a PIA signal to drive into the LAB.Figure 5. MAX3000A PIA Routing
To LABPIA SignalsWhile the routing delays of channel–based routing schemes in masked or FPGAs are cumulative, variable, and path–dependent, the MAX3000A PIA has a predictable delay. The PIA makes a design’s timing performance easy to predict.
I/O Control Blocks
The I/O control block allows each I/O pin to be individually configured for input, output, or bidirectional operation. All I/O pins have a tri–state buffer that is individually controlled by one of the global output enable signals or directly connected to ground or VCC. Figure6 shows the I/O control block for MAX3000A devices. The I/O control block has 6 or 10global output enable signals that are driven by the true or complement of two output enable signals, a subset of the I/O pins, or a subset of the I/O macrocells.
Altera Corporation
MAX 3000A Programmable Logic Device Family Data Sheet
Figure 6. I/O Control Block of MAX3000A Devices
6 or 10 GlobalOutput Enable Signals (1)PIAOE Select MultiplexerVCCto Other I/O PinsfromMacrocellGNDOpen-Drain OutputSlew-Rate Controlto PIANote:(1)
EPM3032A, EPM3064A, EPM3128A, and EPM3256A devices have six output enables. EPM3512A devices have 10output enables.
When the tri–state buffer control is connected to ground, the output is tri-stated (high impedance), and the I/O pin can be used as a dedicated input. When the tri–state buffer control is connected to VCC, the output is enabled.
The MAX3000A architecture provides dual I/O feedback, in which macrocell and pin feedbacks are independent. When an I/O pin is
configured as an input, the associated macrocell can be used for buried logic.
Altera Corporation 11
MAX 3000A Programmable Logic Device Family Data Sheet
In–System Programma-bility
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Programming with External Hardware
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12
MAX3000A devices can be programmed in–system via an industry–standard four–pin IEEE Std. 1149.1-1990 (JTAG) interface. In-system programmability (ISP) offers quick, efficient iterations during design development and debugging cycles. The MAX3000A architecture
internally generates the high programming voltages required to program its EEPROM cells, allowing in–system programming with only a single 3.3–V power supply. During in–system programming, the I/O pins are tri–stated and weakly pulled–up to eliminate board conflicts. The pull–up value is nominally 50 kΩ.
MAX3000A devices have an enhanced ISP algorithm for faster
programming. These devices also offer an ISP_Done bit that ensures safe operation when in–system programming is interrupted. This ISP_Done bit, which is the last bit programmed, prevents all I/O pins from driving until the bit is programmed.
ISP simplifies the manufacturing flow by allowing devices to be mounted on a printed circuit board (PCB) with standard pick–and–place equipment before they are programmed. MAX3000A devices can be programmed by downloading the information via in–circuit testers, embedded processors, the MasterBlaster communications cable, the ByteBlasterMV parallel port download cable, and the BitBlaster serial download cable. Programming the devices after they are placed on the board eliminates lead damage on high–pin–count packages (e.g., QFP packages) due to device handling. MAX3000A devices can be reprogrammed after a system has already shipped to the field. For example, product upgrades can be performed in the field via software or modem.
The Jam STAPL programming and test language can be used to program MAX3000A devices with in–circuit testers, PCs, or embedded processors.
For more information on using the Jam STAPL programming and test language, see Application Note 88 (Using the Jam Language for ISP & ICR via an Embedded Processor), Application Note 122 (Using Jam STAPL for ISP & ICR via an Embedded Processor) and AN 111 (Embedded Programming Using the 8051 and Jam Byte-Code).
The ISP circuitry in MAX3000A devices is compliant with the IEEE Std. 1532 specification. The IEEE Std. 1532 is a standard developed to allow concurrent ISP between multiple PLD vendors.
MAX3000A devices can be programmed on Windows–based PCs with an Altera Logic Programmer card, MPU, and the appropriate device adapter. The MPU performs continuity checking to ensure adequate electrical contact between the adapter and the device.
For more information, see the Altera Programming Hardware Data Sheet.
Altera Corporation
MAX 3000A Programmable Logic Device Family Data Sheet
The Altera software can use text– or waveform–format test vectors created with the Altera Text Editor or Waveform Editor to test the programmed device. For added design verification, designers can perform functional testing to compare the functional device behavior with the results of simulation.
Data I/O, BP Microsystems, and other programming hardware
manufacturers also provide programming support for Altera devices.
f
IEEE Std.
1149.1 (JTAG) Boundary–Scan Support
For more information, see Programming Hardware Manufacturers.
MAX3000A devices include the JTAG BST circuitry defined by IEEE Std.1149.1–1990. Table4 describes the JTAG instructions supported by MAX3000A devices. The pin-out tables found on the Altera web site (http://www.altera.com) or the Altera Digital Library show the location of the JTAG control pins for each device. If the JTAG interface is not required, the JTAG pins are available as user I/O pins.
Table 4.MAX3000A JTAG InstructionsJTAG Instruction
SAMPLE/PRELOADEXTESTBYPASS
Description
Allows a snapshot of signals at the device pins to be captured and examined during normal device operation, and permits an initial data pattern output at the device pinsAllows the external circuitry and board–level interconnections to be tested by forcing a test pattern at the output pins and capturing test results at the input pins
Places the 1–bit bypass register between the TDI and TDO pins, which allows the BST data to pass synchronously through a selected device to adjacent devices during normal device operation
Selects the IDCODE register and places it between the TDI and TDO pins, allowing the IDCODE to be serially shifted out of TDO
Selects the 32–bit USERCODE register and places it between the TDI and TDO pins, allowing the USERCODE value to be shifted out of TDO
These instructions are used when programming MAX3000A devices via the JTAG ports with the MasterBlaster, ByteBlasterMV, or BitBlaster cable, or when using a Jam STAPL file, JBC file, or SVF file via an embedded processor or test equipment
IDCODEUSERCODEISP Instructions
The instruction register length of MAX3000A devices is 10 bits. The IDCODE and USERCODE register length is 32 bits. Tables5 and 6 show the boundary–scan register length and device IDCODE information for MAX3000A devices.
Altera Corporation 13
MAX 3000A Programmable Logic Device Family Data Sheet
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14Table 5.MAX3000A Boundary–Scan Register Length
Device
Boundary–Scan Register Length
EPM3032A96EPM3064A192EPM3128A288EPM3256A480EPM3512A
624
Table 6.32–Bit MAX3000A Device IDCODE ValueNote (1)
Device
IDCODE (32 bits)
Version Part Number (16 Bits)
Manufacturer’s1 (1 Bit) (4 Bits)
Identity (11 Bits)(2)
EPM3032A00010111 0000 0011 0010000011011101EPM3064A00010111 0000 0110 0100000011011101EPM3128A00010111 0001 0010 1000000011011101EPM3256A00010111 0010 0101 0110000011011101EPM3512A0001
0111 0101 0001 0010
00001101110
1
Notes:(1)The most significant bit (MSB) is on the left.
(2)
The least significant bit (LSB) for all JTAG IDCODEs is 1.
See Application Note 39 (IEEE 1149.1 (JTAG) Boundary–Scan Testing in Altera Devices) for more information on JTAG BST.
Altera Corporation
Altera CorporationMAX 3000A Programmable Logic Device Family Data Sheet
Figure7 shows the timing information for the JTAG signals.Figure 7. MAX3000A JTAG Waveforms
TMSTDI tJCP tJCH tJCL tJPSUtJPHTCKtJPZXtJPCOtJPXZTDOtJSSUtJSHSignalCapturedto BetSignalJSZXtJSCOtJSXZDrivento BeTable7 shows the JTAG timing parameters and values for MAX3000A devices.
Table 7.JTAG Timing Parameters & Values for MAX3000A DevicesSymbol
ParameterMin
MaxUnit
tJCPTCK clock period 100nstJCHTCK clock high time 50nstJCLTCK clock low time 50nstJPSUJTAG port setup time 20nstJPHJTAG port hold time 45
ns
tJPCOJTAG port clock to output
25nstJPZXJTAG port high impedance to valid output25nstJPXZJTAG port valid output to high impedance25
nstJSSUCapture register setup time20nstJSHCapture register hold time45
nstJSCOUpdate register clock to output
25nstJSZXUpdate register high impedance to valid output25nstJSXZ
Update register valid output to high impedance
25
ns
15
MAX 3000A Programmable Logic Device Family Data Sheet
Programmable Speed/Power Control
Output
Configuration
16MAX3000A devices offer a power–saving mode that supports low-power operation across user–defined signal paths or the entire device. This feature allows total power dissipation to be reduced by 50% or more because most logic applications require only a small fraction of all gates to operate at maximum frequency.
The designer can program each individual macrocell in a MAX3000A device for either high–speed or low–power operation. As a result, speed-critical paths in the design can run at high speed, while the
remaining paths can operate at reduced power. Macrocells that run at low power incur a nominal timing delay adder (ttLPA) for the tLAD, tLAC, tIC, tACL, EN, tCPPW and tSEXP parameters.
MAX3000A device outputs can be programmed to meet a variety of system–level requirements.
MultiVolt I/O Interface
The MAX3000A device architecture supports the MultiVolt I/O interface feature, which allows MAX3000A devices to connect to systems with differing supply voltages. MAX3000A devices in all packages can be set for 2.5–V, 3.3–V, or 5.0–V I/O pin operation. These devices have one set of VCC pins for internal operation and input buffers (VCCINT), and another set for I/O output drivers (VCCIO).
The VCCIO pins can be connected to either a 3.3–V or 2.5–V power supply, depending on the output requirements. When the VCCIO pins are
connected to a 2.5–V power supply, the output levels are compatible with 2.5–V systems. When the VCCIO pins are connected to a 3.3–V power supply, the output high is at 3.3V and is therefore compatible with 3.3-V or 5.0–V systems. Devices operating with Vincur a nominally greater timing delay of tCCIO levels lower than 3.0V always be driven by 2.5–V, 3.3–V, or 5.0–V signals.
OD2 instead of tOD1. Inputs can Table8 summarizes the MAX3000A MultiVolt I/O support.Table 8.MAX3000A MultiVolt I/O SupportVCCIO Voltage
Input Signal (V)
Output Signal (V)2.5
3.35.02.53.3
5.0
2.5vvvv3.3
v
v
v
v
v
v
Note:(1)
When Vtolerant inputs.
CCIO is 3.3 V, a MAX 3000A device can drive a 2.5–V device that has 3.3–V Altera Corporation
Design Security
Generic Testing
Altera CorporationMAX 3000A Programmable Logic Device Family Data Sheet
Open–Drain Output Option
MAX3000A devices provide an optional open–drain (equivalent to
open-collector) output for each I/O pin. This open–drain output enables the device to provide system–level control signals (e.g., interrupt and write enable signals) that can be asserted by any of several devices. It can also provide an additional wired–OR plane.
Open-drain output pins on MAX3000A devices (with a pull-up resistor to the 5.0-V supply) can drive 5.0-V CMOS input pins that require a high VIH. When the open-drain pin is active, it will drive low. When the pin is inactive, the resistor will pull up the trace to 5.0V, thereby meeting CMOS requirements. The open-drain pin will only drive low or tri-state; it will never drive high. The rise time is dependent on the value of the pull-up resistor and load impedance. The IOL current specification should be considered when selecting a pull-up resistor
Slew–Rate Control
The output buffer for each MAX3000A I/O pin has an adjustable output slew rate that can be configured for low–noise or high–speed
performance. A faster slew rate provides high–speed transitions for
high-performance systems. However, these fast transitions may introduce noise transients into the system. A slow slew rate reduces system noise, but adds a nominal delay of 4 to 5 ns. When the configuration cell is turned off, the slew rate is set for low–noise performance. Each I/O pin has an individual EEPROM bit that controls the slew rate, allowing designers to specify the slew rate on a pin–by–pin basis. The slew rate control affects both the rising and falling edges of the output signal.
All MAX3000A devices contain a programmable security bit that controls access to the data programmed into the device. When this bit is
programmed, a design implemented in the device cannot be copied or retrieved. This feature provides a high level of design security because programmed data within EEPROM cells is invisible. The security bit that controls this function, as well as all other programmed data, is reset only when the device is reprogrammed.
MAX3000A devices are fully tested. Complete testing of each
programmable EEPROM bit and all internal logic elements ensures 100% programming yield. AC test measurements are taken under conditions equivalent to those shown in Figure8. Test patterns can be used and then erased during early stages of the production flow.
17
MAX 3000A Programmable Logic Device Family Data Sheet
Figure 8. MAX3000A AC Test Conditions
Power supply transients can affect ACmeasurements. Simultaneous transitionsof multiple outputs should be avoided foraccurate measurement. Threshold testsmust not be performed under ACconditions. Large–amplitude, fast–
ground–current transients normally occur as the device outputs discharge the load capacitances. When these transients flow through the parasitic inductance between the device ground pin and the test system ground, significant reductions in
observable noise immunity can result. Numbers in brackets are for 2.5–V
outputs. Numbers without brackets are for 3.3–V devices or outputs.
VCC703 Ω[521 Ω]DeviceOutputTo TestSystem620 Ω[481 Ω]Device inputrise and falltimes < 2 nsC1 (includes jigcapacitance)Operating Conditions
Tables9 through 12 provide information on absolute maximum ratings, recommended operating conditions, DC operating conditions, and capacitance for MAX3000A devices.
Note (1)
Min
–0.5–2.0–25
No biasUnder bias
PQFP and TQFP packages, under bias
–65–65
Table 9.MAX3000A Device Absolute Maximum RatingsSymbol
VCCVIIOUTTSTGTATJ
Parameter
Supply voltageDC input voltage
DC output current, per pinStorage temperatureAmbient temperatureJunction temperature
Conditions
With respect to ground (2)
Max
4.65.7525150135135
Unit
VVmA° C° C° C
18Altera Corporation
MAX 3000A Programmable Logic Device Family Data Sheet
Table 10.MAX3000A Device Recommended Operating ConditionsSymbol
VCCINTVCCIO
Parameter
Supply voltage for internal logic and (10)input buffers
Supply voltage for output drivers, 3.3–V operation
Supply voltage for output drivers, 2.5–V operation
ConditionsMin
3.03.02.33.0
Max
3.63.62.73.65.75VCCIO70904040
Unit
VVVVVV° C° Cnsns
VCCISPVIVOTATJtRtF
Supply voltage during ISPInput voltageOutput voltageAmbient temperatureJunction temperatureInput rise timeInput fall time
For commercial useFor commercial use(3)
–0.5000
Table 11.MAX3000A Device DC Operating ConditionsSymbol
VIHVILVOH
Note (4)
Min
1.7–0.5
Parameter
High–level input voltageLow–level input voltage3.3–V high–level TTL output voltage
3.3–V high–level CMOS output voltage
2.5–V high–level output voltage
ConditionsMax
5.750.8
Unit
VVVVVVV
IOH = –8 mA DC, VCCIO = 3.00 V (5)IOH = –0.1 mA DC, VCCIO = 3.00 V (5)IOH = –100 µA DC, VCCIO = 2.30 V (5)IOH = –1 mA DC, VCCIO = 2.30 V (5)IOH = –2 mA DC, VCCIO = 2.30 V (5)
2.4VCCIO – 0.2
2.12.01.7
0.40.20.20.40.7
–10–1020
101074
VOL3.3–V low–level TTL output voltageIOL = 8 mA DC, VCCIO = 3.00 V (6)3.3–V low–level CMOS output voltage
2.5–V low–level output voltage
IOL = 0.1 mA DC, VCCIO = 3.00 V (6)IOL = 100 µA DC, VCCIO = 2.30 V (6)IOL = 1 mA DC, VCCIO = 2.30 V (6)IOL = 2 mA DC, VCCIO = 2.30 V (6)
VVVVVµAµAkΩ
IIIOZRISP
Input leakage current
Tri–state output off–state currentValue of I/O pin pull–up resistor when programming in–system or during power–up
VI = –0.5 to 5.5 V (7)VI = –0.5 to 5.5 V (7)VCCIO = 2.3 to 3.6 V (8)
Altera Corporation 19
MAX 3000A Programmable Logic Device Family Data Sheet
Table 12.MAX3000A Device CapacitanceSymbol
CINCI/O
Note (9)
Conditions
Min
Max
88
Parameter
Input pin capacitanceI/O pin capacitance
Unit
pFpF
VIN = 0 V, f = 1.0 MHzVOUT = 0 V, f = 1.0 MHz
Notes to tables:(1)(2)
See the Operating Requirements for Altera Devices Data Sheet.
Minimum DC input voltage is –0.5 V. During transitions, the inputs may undershoot to –2.0 V or overshoot to 5.75 V for input currents less than 100 mA and periods shorter than 20 ns.
(3)All pins, including dedicated inputs, I/O pins, and JTAG pins, may be driven before VCCINT and VCCIO are
powered.
(4)These values are specified under the recommended operating conditions, as shown in Table10 on page19.
(5)The parameter is measured with 50% of the outputs each sourcing the specified current. The IOH parameter refers
to high–level TTL or CMOS output current.
(6)The parameter is measured with 50% of the outputs each sinking the specified current. The IOL parameter refers to
low–level TTL, PCI, or CMOS output current.
(7)This value is specified during normal device operation. During power-up, the maximum leakage current is
±300µA.
(8)This pull–up exists while devices are programmed in–system and in unprogrammed devices during power–up.(9)Capacitance is measured at 25° C and is sample–tested only. The OE1 pin (high–voltage pin during programming)
has a maximum capacitance of 20 pF.
(10)The POR time for MAX 3000Adevices does not exceed 100ms.
Figure9 shows the typical output drive characteristics of MAX3000A devices.
20Altera Corporation
Power
Sequencing & Hot–Socketing
Altera CorporationMAX 3000A Programmable Logic Device Family Data Sheet
Figure 9. Output Drive Characteristics of MAX3000A Devices
3.3 V150IOLTypical I 100VOutputOCCINT = 3.3 VVCurrent (mA)CCIO = 3.3 VTemperature = 25 C O50IOH001234V2.5 VO Output Voltage (V)150IOLTypical I 100OutputOVCCINT = 3.3 VCurrent (mA)VCCIO = 2.5 VTemperature = 25 C O50IOH001234VO Output Voltage (V)Because MAX3000A devices can be used in a mixed–voltage
environment, they have been designed specifically to tolerate any possible power–up sequence. The Vpowered in any order.
CCIO and VCCINT power planes can be Signals can be driven into MAX3000A devices before and during
power-up without damaging the device. In addition, MAX3000A devices do not drive out during power-up. Once operating conditions are reached, MAX3000A devices operate as specified by the user.
21
MAX 3000A Programmable Logic Device Family Data Sheet
Timing Model
MAX3000A device timing can be analyzed with the Altera software, with a variety of popular industry–standard EDA simulators and timing analyzers, or with the timing model shown in Figure10. MAX3000A devices have predictable internal delays that enable the designer to determine the worst–case timing of any design. The software provides timing simulation, point–to–point delay prediction, and detailed timing analysis for device–wide performance evaluation.
Figure 10. MAX3000A Timing ModelInternal OutputEnable DelaytIOEInputDelaytINPIADelaytPIAGlobal ControlDelaytGLOBLogic ArrayDelaytLADRegisterControl DelaytLACtICtENSharedExpander DelaytSEXPParallelExpander DelaytPEXPRegisterDelaytSUtHtPREtCLRtRDtCOMBOutputDelaytOD1tOD2tOD3tXZtZX1tZX2tZX3I/ODelaytIOThe timing characteristics of any signal path can be derived from the timing model and parameters of a particular device. External timing parameters, which represent pin–to–pin timing delays, can be calculated as the sum of internal parameters. Figure11 shows the timing relationship between internal and external delay parameters.
22Altera Corporation
MAX 3000A Programmable Logic Device Family Data Sheet
Figure 11. MAX3000A Switching Waveforms
tR & tF < 2 ns. Inputs are driven at 3 V for a logic high and 0 V for a logic Combinatorial ModetINlow. All timing characteristics aremeasured at 1.5 V.Altera CorporationInput PintIOI/O PintPIAPIA DelaytSEXPShared ExpanderDelaytLAC , tLADLogic ArrayInputtPEXPParallel ExpanderDelaytLogic ArrayCOMBOutputtODOutput PinGlobal Clock ModeGlobaltRtCHtCLtFClock PintINGlobal ClocktGLOBat RegistertSUtHData or Enable(Logic Array Output)Array Clock ModetRtACHtACLtFInput or I/O PintINtIOClock into PIAClock intotPIALogic ArrayClock attRegisterICtSUtHData fromLogic ArraytRDtPIAtCLR , tPREtPIARegister to PIA to Logic ArraytRegister OutputODtODto Pin 23
MAX 3000A Programmable Logic Device Family Data Sheet
Tables13 through 20 show EPM3032A, EPM3064A, EPM3128A, EPM3256A, and EPM3512A timing information.
Table 13.EPM3032A External Timing ParametersSymbol
Parameter
Conditions
–4Min
tPD1tPD2tSUtHtCO1tCHtCLtASUtAHtACO1tACHtACLtCPPWtCNTfCNTtACNTfACNT
Input to non–registered outputI/O input to non–registered outputGlobal clock setup time
C1 = 35 pF (2)
C1 = 35 pF (2)(2)
2.90.01.02.02.01.60.31.02.02.02.0
4.4
227.3
4.4
227.3
138.9138.9
7.2
103.1
4.3
(2)
C1 = 35 pF (2)
3.0
Note (1)
Speed Grade
–7
Max
4.54.5
4.70.01.03.03.02.50.51.03.03.03.0
7.2
103.1
9.7
7.25.0
Unit
–10
MinMax
7.57.5
MinMax
1010
nsnsnsns
6.7
nsnsnsnsns
9.4
nsnsnsns
9.7
nsMHznsMHz
6.30.01.04.04.03.60.51.04.04.04.0
Global clock hold time(2)Global clock to output C1 = 35 pFdelay
Global clock high timeGlobal clock low timeArray clock setup time(2)Array clock hold timeArray clock to output delay
Array clock high timeArray clock low timeMinimum pulse width (3)for clear and presetMinimum global clock (2)period
Maximum internal (2), (4)global clock frequencyMinimum array clock period
(2)
Maximum internal (2), (4)array clock frequency
24Altera Corporation
MAX 3000A Programmable Logic Device Family Data Sheet
Table 14.EPM3032A Internal Timing Parameters (Part 1 of 2)Symbol
Parameter
Conditions
–4Min
tINtIOtSEXPtPEXPtLADtLACtIOEtOD1
Input pad and buffer delayI/O input pad and buffer delay
Shared expander delayParallel expander delayLogic array delayLogic control array delayInternal output enable delayOutput buffer and pad delay, slow slew rate = offVCCIO = 3.3 V
Output buffer and pad delay, slow slew rate=offVCCIO = 2.5 V
Output buffer and pad delay, slow slew rate = on VCCIO = 2.5 V or 3.3 V
C1 = 35 pF
Note (1)Speed Grade
–7
Max
0.70.71.90.51.50.60.00.8
Unit
–10
MinMax
1.21.23.10.82.51.00.01.3
MinMax
1.51.54.01.03.31.20.01.8
nsnsnsnsnsnsnsns
tOD2
C1 = 35 pF1.31.82.3ns
tOD3
C1 = 35 pF5.86.36.8ns
tZX1
Output buffer enable delay, C1 = 35 pFslow slew rate = off VCCIO = 3.3 V
Output buffer enable delay, C1 = 35 pFslow slew rate = off VCCIO = 2.5 V
Output buffer enable delay, C1 = 35 pFslow slew rate = on VCCIO = 2.5 V or 3.3 V
Output buffer disable delayC1 = 5 pF Register setup timeRegister hold timeRegister delayCombinatorial delayArray clock delayRegister enable timeGlobal control delayRegister preset time
1.30.6
4.04.05.0ns
tZX2
4.54.55.5ns
tZX3
9.09.010.0ns
tXZtSUtHtRDtCOMBtICtENtGLOBtPRE
4.0
2.01.0
0.70.61.20.60.81.2
4.0
2.81.3
1.21.02.01.01.31.9
5.0nsnsns
1.51.32.51.21.92.6
nsnsnsnsnsns
Altera Corporation 25
MAX 3000A Programmable Logic Device Family Data Sheet
Table 14.EPM3032A Internal Timing Parameters (Part 2 of 2)Symbol
Parameter
Conditions
–4Min
tCLRtPIAtLPA
Register clear timePIA delayLow–power adder
(2)(5)
Note (1)Speed Grade
–7
Max
1.20.92.5
Unit
–10
MinMax
1.91.54.0
MinMax
2.62.15.0
nsnsns
Table 15.EPM3064A External Timing ParametersSymbol
Parameter
Conditions
Note (1)
Speed Grade
–4Min
Max
4.54.5
2.80.01.02.02.0
3.1
4.70.01.03.03.02.60.4
4.3
1.03.03.03.0
4.5
222.2
4.5
222.2
135.1135.1
7.4
100.0
7.4
100.0
10.0
7.25.1
Unit
–10
–7Min
Max
7.57.5
6.20.01.04.04.03.60.61.04.04.04.0
MinMax
10.010.0
nsnsnsns
7.0
nsnsnsnsns
9.6
nsnsnsns
10.0
nsMHznsMHz
tPD1tPD2tSUtHtCO1tCHtCLtASUtAHtACO1tACHtACLtCPPWtCNTfCNTtACNTfACNT
Input to non–registered output
C1 = 35 pF (2)
I/O input to non–registered C1 = 35 pF (2)output
Global clock setup timeGlobal clock hold timeGlobal clock high timeGlobal clock low timeArray clock setup timeArray clock hold timeArray clock to output delayArray clock high timeArray clock low timeMinimum pulse width for clear and presetMinimum global clock period
Maximum internal global clock frequencyMaximum internal array clock frequency
(3)(2)(2), (4)(2)(2)
C1 = 35 pF (2)(2)(2)
Global clock to output delayC1 = 35 pF
1.60.31.02.02.02.0
Minimum array clock period(2)
(2), (4)
26Altera Corporation
MAX 3000A Programmable Logic Device Family Data Sheet
Table 16.EPM3064A Internal Timing Parameters (Part 1 of 2)Symbol
Parameter
Conditions
–4Min
tINtIOtSEXPtPEXPtLADtLACtIOEtOD1
Input pad and buffer delayI/O input pad and buffer delay
Shared expander delayParallel expander delayLogic array delayLogic control array delayInternal output enable delayOutput buffer and pad delay, slow slew rate = offVCCIO = 3.3 V
Output buffer and pad delay, slow slew rate=offVCCIO = 2.5 V
Output buffer and pad delay, slow slew rate = on VCCIO = 2.5 V or 3.3 V
C1 = 35 pF
Note (1)Speed Grade
–7
Max
0.60.61.80.41.50.60.00.8
Unit
–10
MinMax
1.11.13.00.72.51.00.01.3
MinMax
1.41.43.90.93.21.20.01.8
nsnsnsnsnsnsnsns
tOD2
C1 = 35 pF1.31.82.3ns
tOD3
C1 = 35 pF5.86.36.8ns
tZX1
Output buffer enable delay, C1 = 35 pFslow slew rate = off VCCIO = 3.3 V
Output buffer enable delay, C1 = 35 pFslow slew rate = off VCCIO = 2.5 V
Output buffer enable delay, C1 = 35 pFslow slew rate = on VCCIO = 2.5 V or 3.3 V
Output buffer disable delayC1 = 5 pF Register setup timeRegister hold timeRegister delayCombinatorial delayArray clock delayRegister enable timeGlobal control delayRegister preset timeRegister clear time
1.30.6
4.04.05.0ns
tZX2
4.54.55.5ns
tZX3
9.09.010.0ns
tXZtSUtHtRDtCOMBtICtENtGLOBtPREtCLR
4.0
2.01.0
0.70.61.20.61.01.31.3
4.0
2.91.3
1.20.91.91.01.52.12.1
5.0nsnsns
1.61.32.51.22.22.92.9
nsnsnsnsnsnsns
Altera Corporation 27
MAX 3000A Programmable Logic Device Family Data Sheet
Table 16.EPM3064A Internal Timing Parameters (Part 2 of 2)Symbol
Parameter
Conditions
–4Min
tPIAtLPA
PIA delayLow–power adder
(2)(5)
Note (1)Speed Grade
–7
Max
1.03.5
Unit
–10
MinMax
1.74.0
MinMax
2.35.0
nsns
Table 17.EPM3128A External Timing ParametersSymbol
Parameter
Conditions
Note (1)
Speed Grade
–5
–7
Max
5.05.0
Unit
–10
Min
tPD1tPD2tSUtHtCO1tCHtCLtASUtAHtACO1tACHtACLtCPPWtCNTfCNTtACNTfACNT
Input to non–registered outputI/O input to non–registered outputGlobal clock setup time
C1 = 35 pF (2)
C1 = 35 pF (2)(2)
3.30.01.02.02.01.80.21.02.02.02.0
(2)
C1 = 35 pF (2)
MinMax
7.57.5
MinMax
1010
nsnsnsns
6.6
nsnsnsnsns
9.4
nsnsnsns
10.2
nsMHz
10.2
nsMHz
4.90.0
3.4
1.03.03.02.80.3
4.9
1.03.03.03.0
5.2
7.7
129.9
5.2
7.7
129.9
7.15.0
6.60.01.04.04.03.80.41.04.04.04.0
Global clock hold time(2)Global clock to output C1 = 35 pFdelay
Global clock high timeGlobal clock low timeArray clock setup time(2)Array clock hold timeArray clock to output delay
Array clock high timeArray clock low timeMinimum pulse width (3)for clear and presetMinimum global clock (2)period
Maximum internal (2), (4)global clock frequencyMinimum array clock period
(2)
192.398.0
Maximum internal (2), (4)array clock frequency
192.398.0
28Altera Corporation
MAX 3000A Programmable Logic Device Family Data Sheet
Table 18.EPM3128A Internal Timing Parameters (Part 1 of 2)Symbol
Parameter
Conditions
–5Min
tINtIOtSEXPtPEXPtLADtLACtIOEtOD1
Input pad and buffer delayI/O input pad and buffer delay
Shared expander delayParallel expander delayLogic array delayLogic control array delayInternal output enable delayOutput buffer and pad delay, slow slew rate = offVCCIO = 3.3 V
Output buffer and pad delay, slow slew rate=offVCCIO = 2.5 V
Output buffer and pad delay, slow slew rate = on VCCIO = 2.5 V or 3.3 V
C1 = 35 pF
Note (1)Speed Grade
–7
Max
0.70.72.00.41.60.70.00.8
Unit
–10
MinMax
1.01.02.90.72.41.00.01.2
MinMax
1.41.43.80.93.11.30.01.6
nsnsnsnsnsnsnsns
tOD2
C1 = 35 pF1.31.72.1ns
tOD3
C1 = 35 pF5.86.26.6ns
tZX1
Output buffer enable delay, C1 = 35 pFslow slew rate = off VCCIO = 3.3 V
Output buffer enable delay, C1 = 35 pFslow slew rate = off VCCIO = 2.5 V
Output buffer enable delay, C1 = 35 pFslow slew rate = on VCCIO = 2.5 V or 3.3 V
Output buffer disable delayC1 = 5 pF Register setup timeRegister hold timeRegister delayCombinatorial delayArray clock delayRegister enable timeGlobal control delayRegister preset timeRegister clear time
1.40.6
4.04.05.0ns
tZX2
4.54.55.5ns
tZX3
9.09.010.0ns
tXZtSUtHtRDtCOMBtICtENtGLOBtPREtCLR
4.0
2.11.0
0.80.51.20.71.11.41.4
4.0
2.91.3
1.20.91.71.01.62.02.0
5.0nsnsns
1.61.32.21.32.02.72.7
nsnsnsnsnsnsns
Altera Corporation 29
MAX 3000A Programmable Logic Device Family Data Sheet
Table 18.EPM3128A Internal Timing Parameters (Part 2 of 2)Symbol
Parameter
Conditions
–5Min
tPIAtLPA
PIA delayLow–power adder
(2)(5)
Note (1)Speed Grade
–7
Max
1.44.0
Unit
–10
MinMax
2.04.0
MinMax
2.65.0
nsns
Table 19.EPM3256A External Timing ParametersSymbol
Parameter
Conditions
Note (1)
Speed Grade
–5
–7
Max
5.55.5
Unit
–10
Min
tPD1tPD2tSUtHtCO1tCHtCLtASUtAHtACO1tACHtACLtCPPWtCNTfCNTtACNTfACNT
Input to non–registered outputI/O input to non–registered outputGlobal clock setup time
C1 = 35 pF (2)
C1 = 35 pF (2)(2)
3.90.01.02.02.02.00.21.02.02.02.0
(2)
C1 = 35 pF (2)
MinMax
7.57.5
MinMax
1010
nsnsnsns
6.4
nsnsnsnsns
9.7
nsnsnsns
10.5
nsMHz
10.5
nsMHz
5.20.0
3.5
1.03.03.02.70.3
5.4
1.03.03.03.0
5.8
7.9
126.6
5.8
7.9
126.6
7.34.8
6.90.01.04.04.03.60.51.04.04.04.0
Global clock hold time(2)Global clock to output C1 = 35 pFdelay
Global clock high timeGlobal clock low timeArray clock setup time(2)Array clock hold timeArray clock to output delay
Array clock high timeArray clock low timeMinimum pulse width (3)for clear and presetMinimum global clock (2)period
Maximum internal (2), (4)global clock frequencyMinimum array clock period
(2)
172.495.2
Maximum internal (2), (4)array clock frequency
172.495.2
30Altera Corporation
MAX 3000A Programmable Logic Device Family Data Sheet
Table 20.EPM3256A Internal Timing Parameters (Part 1 of 2)Symbol
Parameter
Conditions
–5Min
tINtIOtSEXPtPEXPtLADtLACtIOEtOD1
Input pad and buffer delayI/O input pad and buffer delay
Shared expander delayParallel expander delayLogic array delayLogic control array delayInternal output enable delayOutput buffer and pad delay, slow slew rate = offVCCIO = 3.3 V
Output buffer and pad delay, slow slew rate=offVCCIO = 2.5 V
Output buffer and pad delay, slow slew rate = on VCCIO = 2.5 V or 3.3 V
C1 = 35 pF
Note (1)Speed Grade
–7
Max
0.70.72.10.31.70.80.00.9
Unit
–10
MinMax
0.90.92.80.52.21.00.01.2
MinMax
1.21.23.70.62.81.30.01.6
nsnsnsnsnsnsnsns
tOD2
C1 = 35 pF1.41.72.1ns
tOD3
C1 = 35 pF5.96.26.6ns
tZX1
Output buffer enable delay, C1 = 35 pFslow slew rate = off VCCIO = 3.3 V
Output buffer enable delay, C1 = 35 pFslow slew rate = off VCCIO = 2.5 V
Output buffer enable delay, C1 = 35 pFslow slew rate = on VCCIO = 2.5 V or 3.3 V
Output buffer disable delayC1 = 5 pF Register setup timeRegister hold timeRegister delayCombinatorial delayArray clock delayRegister enable timeGlobal control delayRegister preset time
1.50.7
4.04.05.0ns
tZX2
4.54.55.5ns
tZX3
9.09.010.0ns
tXZtSUtHtRDtCOMBtICtENtGLOBtPRE
4.0
2.10.9
0.90.51.20.81.01.6
4.0
2.91.2
1.20.81.61.01.52.3
5.0nsnsns
1.61.22.11.32.03.0
nsnsnsnsnsns
Altera Corporation 31
MAX 3000A Programmable Logic Device Family Data Sheet
Table 20.EPM3256A Internal Timing Parameters (Part 2 of 2)Symbol
Parameter
Conditions
–5Min
tCLRtPIAtLPA
Register clear timePIA delayLow–power adder
(2)(5)
Note (1)Speed Grade
–7
Max
1.61.74.0
Unit
–10
MinMax
2.32.44.0
MinMax
3.03.25.0
nsnsns
Table 21.EPM3512A External Timing ParametersSymbol
Parameter
Note (1)
Speed Grade-7Min
Max
7.57.5
5.60.03.00.0
7.60.03.00.0
4.7
1.04.04.03.50.3
7.8
1.04.04.04.0
8.6
116.3
8.6
116.3
87.087.0
11.511.510.46.3
ConditionsUnit
-10
MinMax
10.010.0
nsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsMHznsMHz
tPD1tPD2tSUtHtFSUtFHtCO1tCHtCLtASUtAHtACO1tACHtACLtCPPWtCNTfCNTtACNTfACNT
Input to non-registered outputI/O input to non-registered output
Global clock setup timeGlobal clock hold timeGlobal clock setup time of fast input
Global clock hold time of fast input
Global clock to output delayGlobal clock high timeGlobal clock low timeArray clock setup timeArray clock hold timeArray clock to output delayArray clock high timeArray clock low time
C1 = 35 pF (2)C1 = 35 pF (2)(2)(2)
C1 = 35 pF1.03.03.0
(2)(2)
C1 = 35 pF (2)
2.50.21.03.03.03.0
Minimum pulse width for clear (3)and preset
Minimum global clock period
(2)
Maximum internal global clock (2), (4)frequency
Minimum array clock periodMaximum internal array clock frequency
(2)(2), (4)
32Altera Corporation
MAX 3000A Programmable Logic Device Family Data Sheet
Table 22.EPM3512A Internal Timing Parameters (Part 1 of 2)Symbol
Parameter
Conditions
Note (1)
Speed Grade-7
-10
Max
0.70.73.12.70.42.21.00.0
Unit
Min
tINtIOtFINtSEXPtPEXPtLADtLACtIOEtOD1
Input pad and buffer delayI/O input pad and buffer delayFast input delayShared expander delayParallel expander delayLogic array delayLogic control array delayInternal output enable delayOutput buffer and pad delay, slow slew rate = offVCCIO = 3.3 V
Output buffer and pad delay, slow slew rate=offVCCIO = 2.5 V
Output buffer and pad delay, slow slew rate = on VCCIO = 2.5 V or 3.3 VOutput buffer enable delay, slow slew rate = off VCCIO = 3.3 V
Output buffer enable delay, slow slew rate = off VCCIO = 2.5 V
Output buffer enable delay, slow slew rate = on VCCIO = 3.3 V
Output buffer disable delayRegister setup timeRegister hold time
Register setup time of fast inputRegister hold time of fast inputRegister delayCombinatorial delayArray clock delayRegister enable timeGlobal control delay
C1 = 35 pF
MinMax
0.90.93.63.50.52.81.30.01.5
nsnsnsnsnsnsnsnsns
1.0
tOD2
C1 = 35 pF1.52.0ns
tOD3
C1 = 35 pF6.06.5ns
tZX1
C1 = 35 pF4.05.0ns
tZX2
C1 = 35 pF4.55.5ns
tZX3
C1 = 35 pF9.010.0ns
tXZtSUtHtFSUtFHtRDtCOMBtICtENtGLOB
C1 = 5 pF
2.10.61.61.4
4.0
3.00.81.61.4
1.30.61.81.01.7
5.0nsnsnsnsns
1.70.82.31.32.2
nsnsnsnsns
Altera Corporation 33
MAX 3000A Programmable Logic Device Family Data Sheet
Table 22.EPM3512A Internal Timing Parameters (Part 2 of 2)Symbol
Parameter
Conditions
Note (1)
Speed Grade-7
-10
Max
1.01.0
Unit
Min
tPREtCLRtPIAtLPA(1)(2)(3)
MinMax
1.41.44.05.0
nsnsnsns
Register preset timeRegister clear timePIA delayLow-power adder
(2)(5)
3.04.5
Notes to tables:
These values are specified under the recommended operating conditions, as shown in Table10 on page19. See Figure11 on page23 for more information on switching waveforms.
These values are specified for a PIA fan–out of one LAB (16 macrocells). For each additional LAB fan–out in these devices, add an additional 0.1 ns to the PIA timing value.
This minimum pulse width for preset and clear applies for both global clear and array controls. The tLPA parameter must be added to this minimum width if the clear or reset signal incorporates the tLAD parameter into the signal path.
These parameters are measured with a 16–bit loadable, enabled, up/down counter programmed into each LAB.The tLPA parameter must be added to the tLAD, tLAC, tIC, tEN, tSEXP, tACL, and tCPPW parameters for macrocells running in low–power mode.
(4)(5)
Power
Consumption
Supply power (P) versus frequency (fMAX, in MHz) for MAX3000A devices is calculated with the following equation:P = PINT + PIO = ICCINT × VCC + PIO
The PIO value, which depends on the device output load characteristics and switching frequency, can be calculated using the guidelines given in Application Note 74 (Evaluating Power for Altera Devices).
The ICCINT value depends on the switching frequency and the application logic. The ICCINT value is calculated with the following equation:ICCINT =
(A × MCTON) + [B × (MCDEV – MCTON)] + (C × MCUSED × fMAX × togLC)The parameters in the ICCINT equation are:
34Altera Corporation
Altera CorporationMAX 3000A Programmable Logic Device Family Data Sheet
MCTON=Number of macrocells with the Turbo BitTM option turned on, as reported in the MAX+PLUSII Report File (.rpt)MC=Number of macrocells in the device
MCDEVUSED=Total number of macrocells in the design, as reported in the RPT File
f=Highest clock frequency to the device
togMAXLC=Average percentage of logic cells toggling at each clock (typically 12.5%)
A, B, C
=Constants (shown in Table23)
Table 23.MAX3000A ICC Equation Constants
Device
A
B
C
EPM3032A0.850.360.017EPM3064A0.850.360.017EPM3128A0.850.360.017EPM3256A0.850.360.017EPM3512A
0.85
0.36
0.017
The ICCINT calculation provides an Iconditions using a pattern of a 16–bit, loadable, enabled, up/down
CC estimate based on typical counter in each LAB with no output load. Actual ICC should be verified during operation because this measurement is sensitive to the actual pattern in the device and the environmental operating conditions. Figures12 and 13 show the typical supply current versus frequency for MAX3000A devices.
35
MAX 3000A Programmable Logic Device Family Data Sheet
36Figure 12. ICC vs. Frequency for MAX3000A Devices
EPM3032AVCC = 3.3 VRoom Temperature 706050Typical I CCHigh SpeedActive (mA) 40227.3 MHz3020144.9 MHz10Non-Turbo050100150200250Frequency (MHz)EPM3064AVRoom Temperature CC = 3.3 V140120100Typical I High SpeedActive (mA)CC 80222.2 MHz6040125.0 MHz20Non-Turbo050100150200250ÊFrequency (MHz)Altera Corporation
MAX 3000A Programmable Logic Device Family Data Sheet
Altera CorporationFigure 13. ICC vs. Frequency for MAX 3000A Devices
EPM3128AVCC = 3.3 VRoom Temperature 210180High Speed192.3 MHz150Typical I Active (mA)CC 12090108.7 MHz6030Non-Turbo050100150200250Frequency (MHz)EPM3256AVCC = 3.3 VRoom Temperature350300172.4 MHz250Typical I High SpeedActive (mA)CC 200150102.0 MHz100Non-Turbo50050100150200Frequency (MHz)EPM3512A600VCC = 3.3 V500Room Temperature116.3 MHz400Typical I CCHigh SpeedActive (mA)30020076.3 MHz100Low Power020406080100120140Frequency (MHz) 37
MAX 3000A Programmable Logic Device Family Data Sheet
DevicePin–Outs
See the Altera web site (http://www.altera.com) or the Altera Digital Library for pin–out information.
Figures14 through 18 show the package pin–out diagrams for MAX3000Adevices.
Figure 14. 44–Pin PLCC/TQFP Package Pin–Out Diagram
Package outlines not drawn to scale.
INPUT/OE2/GCLK2INPUT/OE2/GCLK2INPUT/GCLRnINPUT/GCLRnINPUT/GCLK1INPUT/GCLK1INPUT/OE1INPUT/OE1VCC VCC GNDGNDI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OPin 13938373635I/OI/O/TDOI/OGNDVCCI/OI/OI/O/TCKI/OGNDI/OPin 346 5 4 3 2 1 44 43 42 41 40I/O/TDII/OI/OGNDI/OI/OI/O/TMSI/OVCCI/OGND789101112131415161718 19 20 21 22 23 24 25 26 27 28I/OI/OI/OI/OI/OI/OI/OI/OGNDVCCI/OI/OI/OI/OI/OI/OI/OI/OI/OGNDI/O/TDII/OI/OGNDI/OI/OI/O/TMSI/OVCCI/OGNDI/OI/O/TDOI/OGNDVCCI/OI/OI/O/TCKI/OGNDI/OEPM3032AEPM3064A343332313029EPM3032AEPM3064APin 12VCCI/OPin 2344-Pin PLCC44-Pin TQFP38Altera Corporation
MAX 3000A Programmable Logic Device Family Data Sheet
Figure 15. 100–Pin TQFP Package Pin–Out Diagram
Package outline not drawn to scale.
Pin 1Pin 76EPM3064AEPM3128APin 26Pin 51Figure 16. 144–Pin TQFP Package Pin–Out Diagram
Package outline not drawn to scale.
Indicates locationof Pin 1Pin 1 Pin 109EPM3128AEPM3256APin 37Pin 73Altera Corporation 39
MAX 3000A Programmable Logic Device Family Data Sheet
Figure 17. 208–Pin PQFP Package Pin–Out Diagram
Package outline not drawn to scale.
40Pin 1Pin 157EPM3256AEPM3512APin 53Pin 105Altera Corporation
MAX 3000A Programmable Logic Device Family Data Sheet
Figure 18. 256-Pin FineLine BGA Package Pin-Out Diagram
Package outline not drawn to scale.
A1 BallPad CornerIndicatesLocation ofBall A1ABCDEFGHEPM3512A JKLMNPRT16151413121110987654321Revision History
The information contained in the MAX 3000A Programmable Logic Device Data Sheet version 3.0 supersedes information published in previous versions. The following changes were made in the MAX 3000A Programmable Logic Device Data Sheet version 3.0:
■■
Added EPM3512A device.Updated Tables2 and 3.
Altera Corporation 41
MAX 3000A Programmable Logic Device Family Data Sheet
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